From ec230d65608f86c79d3fc3e8f6e75ac859fa45fb Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 31 Jan 2019 20:39:31 +0800 Subject: [PATCH] sayma: move SYSREF DDMTD to the RTM Put RTM Si5324 into bypass mode before running. Needs rework to cut RTM Si5324 reset trace. Needs rework to fix LVDS termination on RTM R310/R313 and R314/R315. Needs uFL jumper cables between RTM "REF LO DIAG" and "CRD AUX CLKIN" (sic). --- artiq/firmware/libboard_artiq/hmc830_7043.rs | 36 ++++++++++---------- artiq/firmware/libboard_artiq/jesd204sync.rs | 2 +- artiq/gateware/targets/sayma_amc.py | 10 ------ artiq/gateware/targets/sayma_rtm.py | 10 ++++++ 4 files changed, 29 insertions(+), 29 deletions(-) diff --git a/artiq/firmware/libboard_artiq/hmc830_7043.rs b/artiq/firmware/libboard_artiq/hmc830_7043.rs index 2a1654134..c4e2882ce 100644 --- a/artiq/firmware/libboard_artiq/hmc830_7043.rs +++ b/artiq/firmware/libboard_artiq/hmc830_7043.rs @@ -169,21 +169,21 @@ pub mod hmc7043 { const HMC_SYSREF_DIV: u16 = SYSREF_DIV*8; // must be <= 4MHz // enabled, divider, output config - const OUTPUT_CONFIG: [(bool, u16, u8); 14] = [ - (true, DAC_CLK_DIV, 0x08), // 0: DAC2_CLK - (true, SYSREF_DIV, 0x08), // 1: DAC2_SYSREF - (true, DAC_CLK_DIV, 0x08), // 2: DAC1_CLK - (true, SYSREF_DIV, 0x08), // 3: DAC1_SYSREF - (false, 0, 0x08), // 4: ADC2_CLK - (false, 0, 0x08), // 5: ADC2_SYSREF - (false, 0, 0x08), // 6: GTP_CLK2 - (true, SYSREF_DIV, 0x10), // 7: FPGA_DAC_SYSREF, LVDS - (true, FPGA_CLK_DIV, 0x08), // 8: GTP_CLK1 - (false, 0, 0x10), // 9: AMC_MASTER_AUX_CLK - (false, 0, 0x10), // 10: RTM_MASTER_AUX_CLK - (true, FPGA_CLK_DIV, 0x10), // 11: FPGA_ADC_SYSREF, LVDS, used for DDMTD RTIO/SYSREF alignment - (false, 0, 0x08), // 12: ADC1_CLK - (false, 0, 0x08), // 13: ADC1_SYSREF + const OUTPUT_CONFIG: [(bool, u16, u8, bool); 14] = [ + (true, DAC_CLK_DIV, 0x08, false), // 0: DAC2_CLK + (true, SYSREF_DIV, 0x08, true), // 1: DAC2_SYSREF + (true, DAC_CLK_DIV, 0x08, false), // 2: DAC1_CLK + (true, SYSREF_DIV, 0x08, true), // 3: DAC1_SYSREF + (false, 0, 0x08, false), // 4: ADC2_CLK + (false, 0, 0x08, true), // 5: ADC2_SYSREF + (false, 0, 0x08, false), // 6: GTP_CLK2 + (true, SYSREF_DIV, 0x10, true), // 7: FPGA_DAC_SYSREF, LVDS + (true, FPGA_CLK_DIV, 0x08, false), // 8: GTP_CLK1 + (false, 0, 0x10, true), // 9: AMC_MASTER_AUX_CLK + (true, FPGA_CLK_DIV, 0x10, true), // 10: RTM_MASTER_AUX_CLK, LVDS, used for DDMTD RTIO/SYSREF alignment + (false, 0, 0x10, true), // 11: FPGA_ADC_SYSREF + (false, 0, 0x08, false), // 12: ADC1_CLK + (false, 0, 0x08, true), // 13: ADC1_SYSREF ]; fn spi_setup() { @@ -311,10 +311,10 @@ pub mod hmc7043 { for channel in 0..OUTPUT_CONFIG.len() { let channel_base = 0xc8 + 0x0a*(channel as u16); - let (enabled, divider, outcfg) = OUTPUT_CONFIG[channel]; + let (enabled, divider, outcfg, is_sysref) = OUTPUT_CONFIG[channel]; if enabled { - if channel % 2 == 0 { + if !is_sysref { // DCLK channel: enable high-performance mode write(channel_base, 0xd1); } else { @@ -328,7 +328,7 @@ pub mod hmc7043 { write(channel_base + 0x2, ((divider & 0xf00) >> 8) as u8); // bypass analog phase shift on DCLK channels to reduce noise - if channel % 2 == 0 { + if !is_sysref { if divider != 0 { write(channel_base + 0x7, 0x00); // enable divider } else { diff --git a/artiq/firmware/libboard_artiq/jesd204sync.rs b/artiq/firmware/libboard_artiq/jesd204sync.rs index 29f533a5a..3d7924374 100644 --- a/artiq/firmware/libboard_artiq/jesd204sync.rs +++ b/artiq/firmware/libboard_artiq/jesd204sync.rs @@ -64,7 +64,7 @@ fn test_ddmtd_stability(raw: bool, tolerance: i32) -> Result<(), &'static str> { let modulo = if raw { RAW_DDMTD_N } else { DDMTD_N }; let measurement = if raw { measure_ddmdt_phase_raw } else { measure_ddmdt_phase }; - let ntests = if raw { 250000 } else { 150 }; + let ntests = if raw { 15000 } else { 150 }; let mut max_pkpk = 0; for _ in 0..32 { diff --git a/artiq/gateware/targets/sayma_amc.py b/artiq/gateware/targets/sayma_amc.py index 734ffa015..5978d2e89 100755 --- a/artiq/gateware/targets/sayma_amc.py +++ b/artiq/gateware/targets/sayma_amc.py @@ -282,11 +282,6 @@ class MasterDAC(MiniSoC, AMPSoC, RTMCommon): self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con) self.csr_devices.append("routing_table") - self.submodules.sysref_ddmtd = jesd204_tools.DDMTD( - platform.request("adc_sysref"), rtio_clk_freq) - self.csr_devices.append("sysref_ddmtd") - platform.add_false_path_constraints(self.ad9154_crg.cd_jesd.clk, - self.sysref_ddmtd.cd_helper.clk) self.submodules.sysref_sampler = jesd204_tools.SysrefSampler( platform.request("dac_sysref"), self.rtio_tsc.coarse_ts) self.csr_devices.append("sysref_sampler") @@ -578,11 +573,6 @@ class Satellite(BaseSoC, RTMCommon): self.config["I2C_BUS_COUNT"] = 1 self.config["HAS_SI5324"] = None - self.submodules.sysref_ddmtd = jesd204_tools.DDMTD( - platform.request("adc_sysref"), rtio_clk_freq) - self.csr_devices.append("sysref_ddmtd") - platform.add_false_path_constraints(self.ad9154_crg.cd_jesd.clk, - self.sysref_ddmtd.cd_helper.clk) self.submodules.sysref_sampler = jesd204_tools.SysrefSampler( platform.request("dac_sysref"), self.rtio_tsc.coarse_ts) self.csr_devices.append("sysref_sampler") diff --git a/artiq/gateware/targets/sayma_rtm.py b/artiq/gateware/targets/sayma_rtm.py index e50656ed9..6a2cdd64f 100755 --- a/artiq/gateware/targets/sayma_rtm.py +++ b/artiq/gateware/targets/sayma_rtm.py @@ -16,6 +16,7 @@ from misoc.integration.wb_slaves import WishboneSlaveManager from misoc.integration.cpu_interface import get_csr_csv from artiq.gateware import serwb +from artiq.gateware import jesd204_tools from artiq import __version__ as artiq_version @@ -176,6 +177,15 @@ class SaymaRTM(Module): platform.request("hmc7043_gpo")) csr_devices.append("hmc7043_gpo") + # DDMTD + self.clock_domains.cd_rtio = ClockDomain(reset_less=True) + rtio_clock_pads = platform.request("si5324_clkout_fabric") + self.specials += Instance("IBUFGDS", i_I=rtio_clock_pads.p, i_IB=rtio_clock_pads.n, + o_O=self.cd_rtio.clk) + self.submodules.sysref_ddmtd = jesd204_tools.DDMTD( + platform.request("rtm_master_aux_clk"), 125e6) + csr_devices.append("sysref_ddmtd") + # AMC/RTM serwb serwb_pads = platform.request("amc_rtm_serwb") platform.add_period_constraint(serwb_pads.clk, 8.)