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gateware.spi: cleanup doc
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@ -166,10 +166,6 @@ class SPIMaster(Module):
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Notes:
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* M = 32 is the data width (width of the data register,
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maximum write bits, maximum read bits)
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* If there is a miso wire in pads, the input and output can be done
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with two signals (a.k.a. 4-wire SPI), else mosi must be used for
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both output and input (a.k.a. 3-wire SPI) and config.half_duplex
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must to be set when reading data is desired.
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* Every transfer consists of a write_length 0-M bit write followed
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by a read_length 0-M bit read.
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* cs_n is asserted at the beginning and deasserted at the end of the
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@ -184,29 +180,37 @@ class SPIMaster(Module):
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"cs_n all deasserted" means "all cs_n bits high".
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* cs is not mandatory in pads. Framing and chip selection can also
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be handled independently through other means.
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* If there is a miso wire in pads, the input and output can be done
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with two signals (a.k.a. 4-wire SPI), else mosi must be used for
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both output and input (a.k.a. 3-wire SPI) and config.half_duplex
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must to be set when reading data is desired.
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* For 4-wire SPI only the sum of read_length and write_length matters.
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The behavior is the same no matter how the total transfer length is
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divided between the two. For 3-wire SPI, the direction of mosi/miso
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is switched from output to input after write_len cycles, at the
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"shift_out" clk edge corresponding to bit write_length + 1 of the
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transfer.
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* The first bit output on mosi is always the MSB/LSB (depending on
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config.lsb_first) of the data register, independent of
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xfer.write_len. The last bit input from miso always ends up in
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the LSB/MSB (respectively) of the data register, independent of
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read_len.
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* For 4-wire SPI only the sum of read_len and write_len matters. The
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behavior is the same no matter how the total transfer length is
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divided between the two. For 3-wire SPI, the direction of mosi/miso
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is switched from output to input after write_len cycles, at the
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"shift_out" clk edge corresponding to bit write_length + 1 of the
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transfer.
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* Data output on mosi in 4-wire SPI during the read cycles is what
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is found in the data register at the time.
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Data in the data register outside the least/most (depending
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on config.lsb_first) significant read_length bits is what is
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seen on miso during the write cycles.
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* The SPI data register is double-buffered: once a transfer completes,
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the previous transfer's read data is available in the data register
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and new write data can be written, queuing a new transfer. Transfers
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submitted this way are chained and executed without deasserting cs.
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* The SPI data register is double-buffered: Once a transfer has
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started, new write data can be written, queuing a new transfer.
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Transfers submitted this way are chained and executed without
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deasserting cs. Once a transfer completes, the previous transfer's
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read data is available in the data register.
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* A wishbone transaction is ack-ed when the transfer has been written
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to the intermediate buffer. It will be started when there are no
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other transactions being executed.
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other transactions being executed. Writes take one cycle when
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there is either no transfer being executed, no data in the
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intermediate buffer, or a transfer just completing. Reads always
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finish in one cycle.
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Transaction Sequence:
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* If desired, write the config register to set up the core.
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@ -215,28 +219,30 @@ class SPIMaster(Module):
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writing triggers the transfer and when the transfer is accepted to
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the inermediate buffer, the write is ack-ed.
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* If desired, read the data register.
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* If desired write xfer and data for the next, chained, transfer
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* If desired, write data for the next, chained, transfer.
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Register address and bit map:
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config (address 2):
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1 offline: all pins high-z (reset=1)
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1 active: cs/transfer active
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1 active: cs/transfer active (read-only)
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1 pending: transfer pending in intermediate buffer, bus writes will
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block
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block (read-only)
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1 cs_polarity: active level of chip select (reset=0)
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1 clk_polarity: idle level for clk (reset=0)
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1 clk_polarity: idle level of clk (reset=0)
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1 clk_phase: first edge after cs assertion to sample data on (reset=0)
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(clk_polarity, clk_phase) == (CPOL, CPHA) in Freescale language.
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(0, 0): idle low, output on falling, input on rising
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(0, 1): idle low, output on rising, input on falling
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(1, 0): idle high, output on rising, input on falling
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(1, 1): idle high, output on falling, input on rising
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There is never a clk edge during a cs edge.
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1 lsb_first: LSB is the first bit on the wire (reset=0)
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1 half_duplex: 3-wire SPI, in/out on mosi (reset=0)
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8 undefined
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8 div_write: counter load value to divide this module's clock
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to the SPI write clk.
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f_clk/f_spi_write == 2*(div_write + 1) (reset=0)
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to generate the SPI write clk (reset=0)
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f_clk/f_spi_write == div_write + 2
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8 div_read: ditto for the read clock
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xfer (address 1):
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@ -338,12 +344,14 @@ class SPIMaster(Module):
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clk_t = TSTriple()
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self.specials += clk_t.get_tristate(pads.clk)
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mosi_t = TSTriple()
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self.specials += mosi_t.get_tristate(pads.mosi)
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self.comb += [
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clk_t.oe.eq(~config.offline),
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clk_t.o.eq((spi.cg.clk & spi.cs) ^ config.clk_polarity),
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]
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mosi_t = TSTriple()
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self.specials += mosi_t.get_tristate(pads.mosi)
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self.comb += [
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mosi_t.oe.eq(~config.offline & spi.cs &
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(spi.oe | ~config.half_duplex)),
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mosi_t.o.eq(spi.reg.o),
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