M-Labs/artiq
2
0
Fork 2
mirror of https://github.com/m-labs/artiq.git synced 2024-12-19 00:16:29 +08:00
Code Issues Projects Releases Wiki Activity

wrpll: separate collector reset

Browse Source
This commit is contained in:
Sebastien Bourdeauducq 2020-11-09 17:57:13 +08:00
parent a97b4633cb
commit ea95d91428
2 changed files with 14 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
artiq/firmware/libboard_artiq/wrpll.rs
View File

@ -485,6 +485,10 @@ fn select_recovered_clock_int(rc: bool) -> Result<(), &'static str> {
csr::wrpll::main_dcxo_gpio_enable_write(0); csr::wrpll::main_dcxo_gpio_enable_write(0);
csr::wrpll::helper_dcxo_errors_write(0xff); csr::wrpll::helper_dcxo_errors_write(0xff);
csr::wrpll::main_dcxo_errors_write(0xff); csr::wrpll::main_dcxo_errors_write(0xff);
csr::wrpll::collector_reset_write(0);
}
clock::spin_us(1_000); // wait for the collector to produce meaningful output
unsafe {
csr::wrpll::filter_reset_write(0); csr::wrpll::filter_reset_write(0);
} }
@ -499,6 +503,7 @@ fn select_recovered_clock_int(rc: bool) -> Result<(), &'static str> {
unsafe { unsafe {
csr::wrpll::filter_reset_write(1); csr::wrpll::filter_reset_write(1);
csr::wrpll::collector_reset_write(1);
} }
clock::spin_us(50_000); clock::spin_us(50_000);
unsafe { unsafe {

12
artiq/gateware/drtio/wrpll/core.py
View File

@ -51,6 +51,7 @@ class FrequencyCounter(Module, AutoCSR):
class WRPLL(Module, AutoCSR): class WRPLL(Module, AutoCSR):
def __init__(self, helper_clk_pads, main_dcxo_i2c, helper_dxco_i2c, ddmtd_inputs, N=15): def __init__(self, helper_clk_pads, main_dcxo_i2c, helper_dxco_i2c, ddmtd_inputs, N=15):
self.helper_reset = CSRStorage(reset=1) self.helper_reset = CSRStorage(reset=1)
self.collector_reset = CSRStorage(reset=1)
self.filter_reset = CSRStorage(reset=1) self.filter_reset = CSRStorage(reset=1)
self.adpll_offset_helper = CSRStorage(24) self.adpll_offset_helper = CSRStorage(24)
self.adpll_offset_main = CSRStorage(24) self.adpll_offset_main = CSRStorage(24)
@ -69,15 +70,20 @@ class WRPLL(Module, AutoCSR):
] ]
self.clock_domains.cd_helper = ClockDomain() self.clock_domains.cd_helper = ClockDomain()
self.clock_domains.cd_collector = ClockDomain()
self.clock_domains.cd_filter = ClockDomain() self.clock_domains.cd_filter = ClockDomain()
self.helper_reset.storage.attr.add("no_retiming") self.helper_reset.storage.attr.add("no_retiming")
self.filter_reset.storage.attr.add("no_retiming") self.filter_reset.storage.attr.add("no_retiming")
self.specials += Instance("IBUFGDS", self.specials += Instance("IBUFGDS",
i_I=helper_clk_pads.p, i_IB=helper_clk_pads.n, i_I=helper_clk_pads.p, i_IB=helper_clk_pads.n,
o_O=self.cd_helper.clk) o_O=self.cd_helper.clk)
self.comb += self.cd_filter.clk.eq(self.cd_helper.clk) self.comb += [
self.cd_collector.clk.eq(self.cd_collector.clk),
self.cd_filter.clk.eq(self.cd_helper.clk),
]
self.specials += [ self.specials += [
AsyncResetSynchronizer(self.cd_helper, self.helper_reset.storage), AsyncResetSynchronizer(self.cd_helper, self.helper_reset.storage),
AsyncResetSynchronizer(self.cd_collector, self.collector_reset.storage),
AsyncResetSynchronizer(self.cd_filter, self.filter_reset.storage) AsyncResetSynchronizer(self.cd_filter, self.filter_reset.storage)
] ]
@ -92,9 +98,9 @@ class WRPLL(Module, AutoCSR):
self.submodules.ddmtd_ref = DDMTD(ddmtd_counter, ddmtd_inputs.rec_clk) self.submodules.ddmtd_ref = DDMTD(ddmtd_counter, ddmtd_inputs.rec_clk)
self.submodules.ddmtd_main = DDMTD(ddmtd_counter, ddmtd_inputs.main_xo) self.submodules.ddmtd_main = DDMTD(ddmtd_counter, ddmtd_inputs.main_xo)
collector_cd = ClockDomainsRenamer("collector")
filter_cd = ClockDomainsRenamer("filter") filter_cd = ClockDomainsRenamer("filter")
helper_cd = ClockDomainsRenamer("helper") self.submodules.collector = collector_cd(Collector(N))
self.submodules.collector = helper_cd(Collector(N))
self.submodules.filter_helper = filter_cd( self.submodules.filter_helper = filter_cd(
thls.make(filters.helper, data_width=48)) thls.make(filters.helper, data_width=48))
self.submodules.filter_main = filter_cd( self.submodules.filter_main = filter_cd(