diff --git a/artiq/gateware/test/drtio/test_full_stack.py b/artiq/gateware/test/drtio/test_full_stack.py
index c8ef2be12..e3c08d630 100644
--- a/artiq/gateware/test/drtio/test_full_stack.py
+++ b/artiq/gateware/test/drtio/test_full_stack.py
@@ -123,10 +123,8 @@ class TestFullStack(unittest.TestCase):
             while status:
                 status = yield from kcsrs.o_status.read()
                 if status & 2:
-                    yield from kcsrs.o_underflow_reset.write(1)
                     raise RTIOUnderflow
                 if status & 4:
-                    yield from kcsrs.o_sequence_error_reset.write(1)
                     raise RTIOSequenceError
                 yield
                 wlen += 1