From e9592105ce8d93e9ab669f7468530414a607e0a3 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Wed, 14 Dec 2016 10:16:45 +0800 Subject: [PATCH] drtio: fix aux controller clock domain mistakes --- artiq/gateware/drtio/aux_controller.py | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/artiq/gateware/drtio/aux_controller.py b/artiq/gateware/drtio/aux_controller.py index e6b0879c9..d74295e2d 100644 --- a/artiq/gateware/drtio/aux_controller.py +++ b/artiq/gateware/drtio/aux_controller.py @@ -20,7 +20,8 @@ class Transmitter(Module, AutoCSR): self.aux_tx = CSR() self.specials.mem = Memory(mem_dw, max_packet//(mem_dw//8)) - converter = stream.Converter(mem_dw, ll_dw) + converter = ClockDomainsRenamer("rtio")( + stream.Converter(mem_dw, ll_dw)) self.submodules += converter # when continuously fed, the Converter outputs data continuously @@ -107,7 +108,8 @@ class Receiver(Module, AutoCSR): mem_dw = max(min_mem_dw, ll_dw) self.specials.mem = Memory(mem_dw, max_packet//(mem_dw//8)) - converter = stream.Converter(ll_dw, mem_dw) + converter = ClockDomainsRenamer("rtio_rx")( + stream.Converter(ll_dw, mem_dw)) self.submodules += converter # when continuously drained, the Converter accepts data continuously