mirror of https://github.com/m-labs/artiq.git
Remove one RTIO out channel to free up some space for travis builds to succeed
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@ -111,7 +111,7 @@ class ARTIQMiniSoC(BaseSoC):
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platform.request("ttl_h_tx_en").eq(1)
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platform.request("ttl_h_tx_en").eq(1)
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]
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]
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rtio_ins = [platform.request("pmt") for i in range(2)]
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rtio_ins = [platform.request("pmt") for i in range(2)]
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rtio_outs = [platform.request("ttl", i) for i in range(6)] + [fud]
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rtio_outs = [platform.request("ttl", i) for i in range(5)] + [fud]
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self.submodules.rtiocrg = _RTIOMiniCRG(platform)
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self.submodules.rtiocrg = _RTIOMiniCRG(platform)
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self.submodules.rtiophy = rtio.phy.SimplePHY(
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self.submodules.rtiophy = rtio.phy.SimplePHY(
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