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https://github.com/m-labs/artiq.git
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DMA: speed up playback
Time reduced from 1.53µs to 1.37µs.
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parent
41c4de4556
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@ -398,19 +398,21 @@ extern fn dma_playback(timestamp: i64, ptr: i32) {
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csr::cri_con::selected_write(0);
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let status = csr::rtio_dma::error_status_read();
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let timestamp = csr::rtio_dma::error_timestamp_read();
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let channel = csr::rtio_dma::error_channel_read();
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if status & rtio::RTIO_O_STATUS_UNDERFLOW != 0 {
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csr::rtio_dma::error_underflow_reset_write(1);
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raise!("RTIOUnderflow",
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"RTIO underflow at {0} mu, channel {1}",
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timestamp as i64, channel as i64, 0)
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}
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if status & rtio::RTIO_O_STATUS_SEQUENCE_ERROR != 0 {
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csr::rtio_dma::error_sequence_error_reset_write(1);
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raise!("RTIOSequenceError",
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"RTIO sequence error at {0} mu, channel {1}",
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timestamp as i64, channel as i64, 0)
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if status != 0 {
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let timestamp = csr::rtio_dma::error_timestamp_read();
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let channel = csr::rtio_dma::error_channel_read();
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if status & rtio::RTIO_O_STATUS_UNDERFLOW != 0 {
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csr::rtio_dma::error_underflow_reset_write(1);
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raise!("RTIOUnderflow",
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"RTIO underflow at {0} mu, channel {1}",
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timestamp as i64, channel as i64, 0)
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}
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if status & rtio::RTIO_O_STATUS_SEQUENCE_ERROR != 0 {
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csr::rtio_dma::error_sequence_error_reset_write(1);
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raise!("RTIOSequenceError",
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"RTIO sequence error at {0} mu, channel {1}",
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timestamp as i64, channel as i64, 0)
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}
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}
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}
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}
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@ -605,7 +605,7 @@ class DMATest(ExperimentCase):
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exp.playback_many(count)
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dt = self.dataset_mgr.get("dma_playback_time")
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print("dt={}, dt/count={}".format(dt, dt/count))
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self.assertLess(dt/count, 7*us)
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self.assertLess(dt/count, 3*us)
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def test_handle_invalidation(self):
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exp = self.create(_DMA)
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