mirror of https://github.com/m-labs/artiq.git
coredevice/exceptions: port to NAC3
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parent
2616e1928d
commit
e8e1ccd4f1
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@ -3,6 +3,8 @@ import logging
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import traceback
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import numpy
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import socket
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import re
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import linecache
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from enum import Enum
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from fractions import Fraction
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from collections import namedtuple
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@ -10,6 +12,8 @@ from collections import namedtuple
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from artiq.coredevice import exceptions
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from artiq.coredevice.comm import initialize_connection
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from artiq import __version__ as software_version
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from artiq.coredevice.runtime import source_loader
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from artiq import __artiq_dir__ as artiq_dir
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logger = logging.getLogger(__name__)
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@ -171,6 +175,98 @@ class CommKernelDummy:
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pass
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class CoreException:
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"""Information about an exception raised or passed through the core device."""
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def __init__(self, exceptions, exception_info, traceback, stack_pointers):
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self.exceptions = exceptions
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self.exception_info = exception_info
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self.traceback = list(traceback)
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self.stack_pointers = stack_pointers
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first_exception = exceptions[0]
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name = first_exception[0]
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if ':' in name:
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exn_id, self.name = name.split(':', 2)
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self.id = int(exn_id)
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else:
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self.id, self.name = 0, name
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self.message = first_exception[1]
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self.params = first_exception[2]
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def append_backtrace(self, record, inlined=False):
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filename, line, column, function, address = record
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stub_globals = {"__name__": filename, "__loader__": source_loader}
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source_line = linecache.getline(filename, line, stub_globals)
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indentation = re.search(r"^\s*", source_line).end()
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if address is None:
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formatted_address = ""
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elif inlined:
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formatted_address = " (inlined)"
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else:
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formatted_address = " (RA=+0x{:x})".format(address)
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filename = filename.replace(artiq_dir, "<artiq>")
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lines = []
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if column == -1:
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lines.append(" {}".format(source_line.strip() if source_line else "<unknown>"))
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lines.append(" File \"{file}\", line {line}, in {function}{address}".
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format(file=filename, line=line, function=function,
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address=formatted_address))
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else:
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lines.append(" {}^".format(" " * (column - indentation)))
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lines.append(" {}".format(source_line.strip() if source_line else "<unknown>"))
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lines.append(" File \"{file}\", line {line}, column {column},"
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" in {function}{address}".
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format(file=filename, line=line, column=column + 1,
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function=function, address=formatted_address))
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return lines
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def single_traceback(self, exception_index):
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# note that we insert in reversed order
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lines = []
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last_sp = 0
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start_backtrace_index = self.exception_info[exception_index][1]
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zipped = list(zip(self.traceback[start_backtrace_index:],
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self.stack_pointers[start_backtrace_index:]))
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exception = self.exceptions[exception_index]
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name = exception[0]
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message = exception[1]
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params = exception[2]
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if ':' in name:
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exn_id, name = name.split(':', 2)
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exn_id = int(exn_id)
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else:
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exn_id = 0
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lines.append("{}({}): {}".format(name, exn_id, message.format(*params)))
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zipped.append(((exception[3], exception[4], exception[5], exception[6],
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None, []), None))
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for ((filename, line, column, function, address, inlined), sp) in zipped:
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# backtrace of nested exceptions may be discontinuous
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# but the stack pointer must increase monotonically
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if sp is not None and sp <= last_sp:
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continue
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last_sp = sp
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for record in reversed(inlined):
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lines += self.append_backtrace(record, True)
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lines += self.append_backtrace((filename, line, column, function,
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address))
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lines.append("Traceback (most recent call first):")
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return "\n".join(reversed(lines))
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def __str__(self):
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tracebacks = [self.single_traceback(i) for i in range(len(self.exceptions))]
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traceback_str = ('\n\nDuring handling of the above exception, ' +
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'another exception occurred:\n\n').join(tracebacks)
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return 'Core Device Traceback:\n' +\
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traceback_str +\
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'\n\nEnd of Core Device Traceback\n'
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class CommKernel:
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warned_of_mismatch = False
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@ -1,162 +1,61 @@
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import builtins
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import linecache
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import re
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import os
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from artiq import __artiq_dir__ as artiq_dir
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from artiq.coredevice.runtime import source_loader
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ZeroDivisionError = builtins.ZeroDivisionError
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ValueError = builtins.ValueError
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IndexError = builtins.IndexError
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RuntimeError = builtins.RuntimeError
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AssertionError = builtins.AssertionError
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class CoreException:
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"""Information about an exception raised or passed through the core device."""
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def __init__(self, exceptions, exception_info, traceback, stack_pointers):
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self.exceptions = exceptions
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self.exception_info = exception_info
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self.traceback = list(traceback)
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self.stack_pointers = stack_pointers
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first_exception = exceptions[0]
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name = first_exception[0]
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if ':' in name:
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exn_id, self.name = name.split(':', 2)
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self.id = int(exn_id)
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else:
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self.id, self.name = 0, name
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self.message = first_exception[1]
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self.params = first_exception[2]
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def append_backtrace(self, record, inlined=False):
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filename, line, column, function, address = record
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stub_globals = {"__name__": filename, "__loader__": source_loader}
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source_line = linecache.getline(filename, line, stub_globals)
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indentation = re.search(r"^\s*", source_line).end()
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if address is None:
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formatted_address = ""
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elif inlined:
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formatted_address = " (inlined)"
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else:
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formatted_address = " (RA=+0x{:x})".format(address)
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filename = filename.replace(artiq_dir, "<artiq>")
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lines = []
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if column == -1:
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lines.append(" {}".format(source_line.strip() if source_line else "<unknown>"))
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lines.append(" File \"{file}\", line {line}, in {function}{address}".
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format(file=filename, line=line, function=function,
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address=formatted_address))
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else:
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lines.append(" {}^".format(" " * (column - indentation)))
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lines.append(" {}".format(source_line.strip() if source_line else "<unknown>"))
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lines.append(" File \"{file}\", line {line}, column {column},"
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" in {function}{address}".
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format(file=filename, line=line, column=column + 1,
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function=function, address=formatted_address))
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return lines
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def single_traceback(self, exception_index):
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# note that we insert in reversed order
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lines = []
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last_sp = 0
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start_backtrace_index = self.exception_info[exception_index][1]
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zipped = list(zip(self.traceback[start_backtrace_index:],
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self.stack_pointers[start_backtrace_index:]))
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exception = self.exceptions[exception_index]
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name = exception[0]
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message = exception[1]
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params = exception[2]
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if ':' in name:
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exn_id, name = name.split(':', 2)
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exn_id = int(exn_id)
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else:
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exn_id = 0
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lines.append("{}({}): {}".format(name, exn_id, message.format(*params)))
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zipped.append(((exception[3], exception[4], exception[5], exception[6],
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None, []), None))
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for ((filename, line, column, function, address, inlined), sp) in zipped:
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# backtrace of nested exceptions may be discontinuous
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# but the stack pointer must increase monotonically
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if sp is not None and sp <= last_sp:
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continue
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last_sp = sp
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for record in reversed(inlined):
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lines += self.append_backtrace(record, True)
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lines += self.append_backtrace((filename, line, column, function,
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address))
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lines.append("Traceback (most recent call first):")
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return "\n".join(reversed(lines))
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def __str__(self):
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tracebacks = [self.single_traceback(i) for i in range(len(self.exceptions))]
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traceback_str = ('\n\nDuring handling of the above exception, ' +
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'another exception occurred:\n\n').join(tracebacks)
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return 'Core Device Traceback:\n' +\
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traceback_str +\
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'\n\nEnd of Code Device Traceback\n'
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class InternalError(Exception):
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"""Raised when the runtime encounters an internal error condition."""
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artiq_builtin = True
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class CacheError(Exception):
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"""Raised when putting a value into a cache row would violate memory safety."""
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artiq_builtin = True
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from artiq.language.core import nac3
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@nac3
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class RTIOUnderflow(Exception):
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"""Raised when the CPU or DMA core fails to submit a RTIO event early
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enough (with respect to the event's timestamp).
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# NAC3TODO """Raised when the CPU or DMA core fails to submit a RTIO event early
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# enough (with respect to the event's timestamp).
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The offending event is discarded and the RTIO core keeps operating.
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"""
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artiq_builtin = True
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# The offending event is discarded and the RTIO core keeps operating.
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# """
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pass
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@nac3
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class RTIOOverflow(Exception):
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"""Raised when at least one event could not be registered into the RTIO
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input FIFO because it was full (CPU not reading fast enough).
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# NAC3TODO """Raised when at least one event could not be registered into the RTIO
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# input FIFO because it was full (CPU not reading fast enough).
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This does not interrupt operations further than cancelling the current
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read attempt and discarding some events. Reading can be reattempted after
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the exception is caught, and events will be partially retrieved.
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"""
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artiq_builtin = True
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# This does not interrupt operations further than cancelling the current
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# read attempt and discarding some events. Reading can be reattempted after
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# the exception is caught, and events will be partially retrieved.
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# """
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pass
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@nac3
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class RTIODestinationUnreachable(Exception):
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"""Raised with a RTIO operation could not be completed due to a DRTIO link
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being down.
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"""
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artiq_builtin = True
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# NAC3TODO """Raised with a RTIO operation could not be completed due to a DRTIO link
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# being down.
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# """
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pass
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@nac3
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class CacheError(Exception):
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# NAC3TODO """Raised when putting a value into a cache row would violate memory safety."""
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pass
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@nac3
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class DMAError(Exception):
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"""Raised when performing an invalid DMA operation."""
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artiq_builtin = True
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# NAC3TODO """Raised when performing an invalid DMA operation."""
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pass
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@nac3
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class ClockFailure(Exception):
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"""Raised when RTIO PLL has lost lock."""
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# NAC3TODO """Raised when RTIO PLL has lost lock."""
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pass
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@nac3
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class I2CError(Exception):
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"""Raised when a I2C transaction fails."""
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# NAC3TODO """Raised when a I2C transaction fails."""
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pass
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@nac3
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class SPIError(Exception):
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"""Raised when a SPI transaction fails."""
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# NAC3TODO """Raised when a SPI transaction fails."""
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pass
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