mirror of https://github.com/m-labs/artiq.git
gateware: merge kasli_generic into kasli. Closes #2279
This commit is contained in:
parent
de10e584f6
commit
e81e8f28cf
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@ -77,6 +77,9 @@ Accesses to the data argument should be replaced as below:
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Refer to the updated ``no_hardware/arguments_demo.py`` example for current usage.
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* Almazny v1.2 is incompatible with the legacy versions and is the default.
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To use legacy versions, specify ``almazny_hw_rev`` in the JSON description.
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* kasli_generic.py has been merged into kasli.py, and the demonstration designs without JSON descriptions
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have been removed. The base classes remain present in kasli.py to support third-party flows without
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JSON descriptions.
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* Legacy PYON databases should be converted to LMDB with the script below:
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::
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@ -1,6 +1,8 @@
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#!/usr/bin/env python3
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import argparse
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import logging
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from packaging.version import Version
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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@ -14,16 +16,20 @@ from misoc.targets.kasli import (
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BaseSoC, MiniSoC, soc_kasli_args, soc_kasli_argdict)
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from misoc.integration.builder import builder_args, builder_argdict
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from artiq import __version__ as artiq_version
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from artiq.gateware.amp import AMPSoC
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from artiq.gateware import rtio
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from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, edge_counter
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from artiq.gateware.rtio.xilinx_clocking import fix_serdes_timing_path
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from artiq.gateware import eem
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from artiq.gateware import rtio, eem, eem_7series
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from artiq.gateware.drtio.transceiver import gtp_7series, eem_serdes
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from artiq.gateware.drtio.siphaser import SiPhaser7Series
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from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
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from artiq.gateware.drtio import *
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from artiq.build_soc import *
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from artiq.coredevice import jsondesc
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logger = logging.getLogger(__name__)
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class SMAClkinForward(Module):
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@ -130,89 +136,6 @@ class StandaloneBase(MiniSoC, AMPSoC):
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self.csr_devices.append("rtio_analyzer")
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class Tester(StandaloneBase):
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"""
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Configuration for CI tests. Contains the maximum number of different EEMs.
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"""
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def __init__(self, hw_rev=None, dds=None, **kwargs):
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if hw_rev is None:
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hw_rev = "v2.0"
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if dds is None:
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dds = "ad9910"
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StandaloneBase.__init__(self, hw_rev=hw_rev, **kwargs)
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# self.config["SI5324_EXT_REF"] = None
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self.config["RTIO_FREQUENCY"] = "125.0"
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if hw_rev == "v1.0":
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# EEM clock fan-out from Si5324, not MMCX
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self.comb += self.platform.request("clk_sel").eq(1)
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self.rtio_channels = []
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eem.DIO.add_std(self, 5,
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ttl_serdes_7series.InOut_8X, ttl_serdes_7series.Output_8X,
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edge_counter_cls=edge_counter.SimpleEdgeCounter)
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eem.Urukul.add_std(self, 0, 1, ttl_serdes_7series.Output_8X, dds,
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ttl_simple.ClockGen)
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eem.Sampler.add_std(self, 3, 2, ttl_serdes_7series.Output_8X)
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eem.Zotino.add_std(self, 4, ttl_serdes_7series.Output_8X)
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if hw_rev in ("v1.0", "v1.1"):
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for i in (1, 2):
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sfp_ctl = self.platform.request("sfp_ctl", i)
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phy = ttl_simple.Output(sfp_ctl.led)
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self.submodules += phy
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self.rtio_channels.append(rtio.Channel.from_phy(phy))
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self.config["HAS_RTIO_LOG"] = None
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self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
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self.rtio_channels.append(rtio.LogChannel())
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self.add_rtio(self.rtio_channels)
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class SUServo(StandaloneBase):
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"""
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SUServo (Sampler-Urukul-Servo) extension variant configuration
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"""
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def __init__(self, hw_rev=None, **kwargs):
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if hw_rev is None:
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hw_rev = "v2.0"
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StandaloneBase.__init__(self, hw_rev=hw_rev, **kwargs)
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# self.config["SI5324_EXT_REF"] = None
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self.config["RTIO_FREQUENCY"] = "125.0"
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if hw_rev == "v1.0":
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# EEM clock fan-out from Si5324, not MMCX
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self.comb += self.platform.request("clk_sel").eq(1)
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self.rtio_channels = []
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# EEM0, EEM1: DIO
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eem.DIO.add_std(self, 0,
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ttl_serdes_7series.InOut_8X, ttl_serdes_7series.Output_8X)
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eem.DIO.add_std(self, 1,
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ttl_serdes_7series.Output_8X, ttl_serdes_7series.Output_8X)
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# EEM3/2: Sampler, EEM5/4: Urukul, EEM7/6: Urukul
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eem.SUServo.add_std(self,
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eems_sampler=(3, 2),
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eems_urukul=[[5, 4], [7, 6]])
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for i in (1, 2):
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sfp_ctl = self.platform.request("sfp_ctl", i)
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phy = ttl_simple.Output(sfp_ctl.led)
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self.submodules += phy
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self.rtio_channels.append(rtio.Channel.from_phy(phy))
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self.config["HAS_RTIO_LOG"] = None
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self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
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self.rtio_channels.append(rtio.LogChannel())
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self.add_rtio(self.rtio_channels)
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pads = self.platform.lookup_request("sampler3_adc_data_p")
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self.platform.add_false_path_constraints(
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pads.clkout, self.crg.cd_sys.clk)
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class MasterBase(MiniSoC, AMPSoC):
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mem_map = {
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"cri_con": 0x10000000,
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@ -640,77 +563,184 @@ class SatelliteBase(BaseSoC, AMPSoC):
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self.get_native_sdram_if(), cpu_dw=self.cpu_dw)
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self.csr_devices.append("rtio_analyzer")
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class Master(MasterBase):
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def __init__(self, hw_rev=None, **kwargs):
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class GenericStandalone(StandaloneBase):
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def __init__(self, description, hw_rev=None,**kwargs):
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if hw_rev is None:
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hw_rev = "v2.0"
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MasterBase.__init__(self, hw_rev=hw_rev, **kwargs)
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hw_rev = description["hw_rev"]
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self.class_name_override = description["variant"]
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StandaloneBase.__init__(self, hw_rev=hw_rev, **kwargs)
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self.config["RTIO_FREQUENCY"] = "{:.1f}".format(description["rtio_frequency"]/1e6)
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if "ext_ref_frequency" in description:
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self.config["SI5324_EXT_REF"] = None
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self.config["EXT_REF_FREQUENCY"] = "{:.1f}".format(
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description["ext_ref_frequency"]/1e6)
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if hw_rev == "v1.0":
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# EEM clock fan-out from Si5324, not MMCX
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self.comb += self.platform.request("clk_sel").eq(1)
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has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"])
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if has_grabber:
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self.grabber_csr_group = []
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self.rtio_channels = []
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phy = ttl_simple.Output(self.platform.request("user_led", 0))
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self.submodules += phy
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self.rtio_channels.append(rtio.Channel.from_phy(phy))
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# matches Tester EEM numbers
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eem.DIO.add_std(self, 5,
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ttl_serdes_7series.InOut_8X, ttl_serdes_7series.Output_8X)
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eem.Urukul.add_std(self, 0, 1, ttl_serdes_7series.Output_8X)
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eem_7series.add_peripherals(self, description["peripherals"])
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if hw_rev in ("v1.0", "v1.1"):
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for i in (1, 2):
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print("SFP LED at RTIO channel 0x{:06x}".format(len(self.rtio_channels)))
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sfp_ctl = self.platform.request("sfp_ctl", i)
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phy = ttl_simple.Output(sfp_ctl.led)
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self.submodules += phy
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self.rtio_channels.append(rtio.Channel.from_phy(phy))
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if hw_rev in ("v1.1", "v2.0"):
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for i in range(3):
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print("USER LED at RTIO channel 0x{:06x}".format(len(self.rtio_channels)))
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phy = ttl_simple.Output(self.platform.request("user_led", i))
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self.submodules += phy
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self.rtio_channels.append(rtio.Channel.from_phy(phy))
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self.config["HAS_RTIO_LOG"] = None
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self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
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self.rtio_channels.append(rtio.LogChannel())
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self.add_rtio(self.rtio_channels)
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self.add_rtio(self.rtio_channels, sed_lanes=description["sed_lanes"])
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if has_grabber:
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self.config["HAS_GRABBER"] = None
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self.add_csr_group("grabber", self.grabber_csr_group)
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for grabber in self.grabber_csr_group:
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self.platform.add_false_path_constraints(
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self.crg.cd_sys.clk, getattr(self, grabber).deserializer.cd_cl.clk)
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class Satellite(SatelliteBase):
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def __init__(self, hw_rev=None, **kwargs):
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class GenericMaster(MasterBase):
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def __init__(self, description, hw_rev=None, **kwargs):
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if hw_rev is None:
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hw_rev = "v2.0"
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SatelliteBase.__init__(self, hw_rev=hw_rev, **kwargs)
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hw_rev = description["hw_rev"]
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self.class_name_override = description["variant"]
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has_drtio_over_eem = any(peripheral["type"] == "shuttler" for peripheral in description["peripherals"])
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MasterBase.__init__(self,
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hw_rev=hw_rev,
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rtio_clk_freq=description["rtio_frequency"],
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enable_sata=description["enable_sata_drtio"],
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enable_sys5x=has_drtio_over_eem,
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**kwargs)
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if "ext_ref_frequency" in description:
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self.config["SI5324_EXT_REF"] = None
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self.config["EXT_REF_FREQUENCY"] = "{:.1f}".format(
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description["ext_ref_frequency"]/1e6)
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if hw_rev == "v1.0":
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# EEM clock fan-out from Si5324, not MMCX
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self.comb += self.platform.request("clk_sel").eq(1)
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if has_drtio_over_eem:
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self.eem_drtio_channels = []
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has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"])
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if has_grabber:
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self.grabber_csr_group = []
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self.rtio_channels = []
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phy = ttl_simple.Output(self.platform.request("user_led", 0))
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self.submodules += phy
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self.rtio_channels.append(rtio.Channel.from_phy(phy))
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# matches Tester EEM numbers
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eem.DIO.add_std(self, 5,
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ttl_serdes_7series.InOut_8X, ttl_serdes_7series.Output_8X)
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eem_7series.add_peripherals(self, description["peripherals"])
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if hw_rev in ("v1.1", "v2.0"):
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for i in range(3):
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print("USER LED at RTIO channel 0x{:06x}".format(len(self.rtio_channels)))
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phy = ttl_simple.Output(self.platform.request("user_led", i))
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self.submodules += phy
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self.rtio_channels.append(rtio.Channel.from_phy(phy))
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self.add_rtio(self.rtio_channels)
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self.config["HAS_RTIO_LOG"] = None
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self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
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self.rtio_channels.append(rtio.LogChannel())
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if has_drtio_over_eem:
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self.add_eem_drtio(self.eem_drtio_channels)
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self.add_drtio_cpuif_groups()
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self.add_rtio(self.rtio_channels, sed_lanes=description["sed_lanes"])
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if has_grabber:
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self.config["HAS_GRABBER"] = None
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self.add_csr_group("grabber", self.grabber_csr_group)
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for grabber in self.grabber_csr_group:
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self.platform.add_false_path_constraints(
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self.gt_drtio.gtps[0].txoutclk, getattr(self, grabber).deserializer.cd_cl.clk)
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VARIANTS = {cls.__name__.lower(): cls for cls in [Tester, SUServo, Master, Satellite]}
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class GenericSatellite(SatelliteBase):
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def __init__(self, description, hw_rev=None, **kwargs):
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if hw_rev is None:
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hw_rev = description["hw_rev"]
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self.class_name_override = description["variant"]
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SatelliteBase.__init__(self,
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hw_rev=hw_rev,
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rtio_clk_freq=description["rtio_frequency"],
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enable_sata=description["enable_sata_drtio"],
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**kwargs)
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if hw_rev == "v1.0":
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# EEM clock fan-out from Si5324, not MMCX
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self.comb += self.platform.request("clk_sel").eq(1)
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has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"])
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if has_grabber:
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self.grabber_csr_group = []
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self.rtio_channels = []
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eem_7series.add_peripherals(self, description["peripherals"])
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if hw_rev in ("v1.1", "v2.0"):
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for i in range(3):
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print("USER LED at RTIO channel 0x{:06x}".format(len(self.rtio_channels)))
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phy = ttl_simple.Output(self.platform.request("user_led", i))
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self.submodules += phy
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self.rtio_channels.append(rtio.Channel.from_phy(phy))
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self.config["HAS_RTIO_LOG"] = None
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self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
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self.rtio_channels.append(rtio.LogChannel())
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self.add_rtio(self.rtio_channels, sed_lanes=description["sed_lanes"])
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if has_grabber:
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self.config["HAS_GRABBER"] = None
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self.add_csr_group("grabber", self.grabber_csr_group)
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for grabber in self.grabber_csr_group:
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self.platform.add_false_path_constraints(
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self.gt_drtio.gtps[0].txoutclk, getattr(self, grabber).deserializer.cd_cl.clk)
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def main():
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parser = argparse.ArgumentParser(
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description="ARTIQ device binary builder for Kasli systems")
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description="ARTIQ device binary builder for generic Kasli systems")
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builder_args(parser)
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soc_kasli_args(parser)
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parser.set_defaults(output_dir="artiq_kasli")
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parser.add_argument("-V", "--variant", default="tester",
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help="variant: {} (default: %(default)s)".format(
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"/".join(sorted(VARIANTS.keys()))))
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parser.add_argument("--tester-dds", default=None,
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help="Tester variant DDS type: ad9910/ad9912 "
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"(default: ad9910)")
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parser.add_argument("description", metavar="DESCRIPTION",
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help="JSON system description file")
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parser.add_argument("--gateware-identifier-str", default=None,
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help="Override ROM identifier")
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args = parser.parse_args()
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description = jsondesc.load(args.description)
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argdict = dict()
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argdict["gateware_identifier_str"] = args.gateware_identifier_str
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argdict["dds"] = args.tester_dds
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min_artiq_version = description["min_artiq_version"]
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if Version(artiq_version) < Version(min_artiq_version):
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logger.warning("ARTIQ version mismatch: current %s < %s minimum",
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artiq_version, min_artiq_version)
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variant = args.variant.lower()
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try:
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cls = VARIANTS[variant]
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except KeyError:
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raise SystemExit("Invalid variant (-V/--variant)")
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if description["target"] != "kasli":
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raise ValueError("Description is for a different target")
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soc = cls(**soc_kasli_argdict(args), **argdict)
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if description["drtio_role"] == "standalone":
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cls = GenericStandalone
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elif description["drtio_role"] == "master":
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cls = GenericMaster
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elif description["drtio_role"] == "satellite":
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cls = GenericSatellite
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else:
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raise ValueError("Invalid DRTIO role")
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has_shuttler = any(peripheral["type"] == "shuttler" for peripheral in description["peripherals"])
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if has_shuttler and (description["drtio_role"] == "standalone"):
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raise ValueError("Shuttler requires DRTIO, please switch role to master")
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soc = cls(description, gateware_identifier_str=args.gateware_identifier_str, **soc_kasli_argdict(args))
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args.variant = description["variant"]
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build_artiq_soc(soc, builder_argdict(args))
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@ -1,201 +0,0 @@
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#!/usr/bin/env python3
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import argparse
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import logging
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from packaging.version import Version
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from misoc.integration.builder import builder_args, builder_argdict
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from misoc.targets.kasli import soc_kasli_args, soc_kasli_argdict
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from artiq import __version__ as artiq_version
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from artiq.coredevice import jsondesc
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from artiq.gateware import rtio, eem_7series
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from artiq.gateware.rtio.phy import ttl_simple
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from artiq.gateware.targets.kasli import StandaloneBase, MasterBase, SatelliteBase
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from artiq.build_soc import *
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logger = logging.getLogger(__name__)
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class GenericStandalone(StandaloneBase):
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def __init__(self, description, hw_rev=None,**kwargs):
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if hw_rev is None:
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hw_rev = description["hw_rev"]
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self.class_name_override = description["variant"]
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StandaloneBase.__init__(self, hw_rev=hw_rev, **kwargs)
|
||||
self.config["RTIO_FREQUENCY"] = "{:.1f}".format(description["rtio_frequency"]/1e6)
|
||||
if "ext_ref_frequency" in description:
|
||||
self.config["SI5324_EXT_REF"] = None
|
||||
self.config["EXT_REF_FREQUENCY"] = "{:.1f}".format(
|
||||
description["ext_ref_frequency"]/1e6)
|
||||
if hw_rev == "v1.0":
|
||||
# EEM clock fan-out from Si5324, not MMCX
|
||||
self.comb += self.platform.request("clk_sel").eq(1)
|
||||
|
||||
has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"])
|
||||
if has_grabber:
|
||||
self.grabber_csr_group = []
|
||||
|
||||
self.rtio_channels = []
|
||||
eem_7series.add_peripherals(self, description["peripherals"])
|
||||
if hw_rev in ("v1.0", "v1.1"):
|
||||
for i in (1, 2):
|
||||
print("SFP LED at RTIO channel 0x{:06x}".format(len(self.rtio_channels)))
|
||||
sfp_ctl = self.platform.request("sfp_ctl", i)
|
||||
phy = ttl_simple.Output(sfp_ctl.led)
|
||||
self.submodules += phy
|
||||
self.rtio_channels.append(rtio.Channel.from_phy(phy))
|
||||
if hw_rev in ("v1.1", "v2.0"):
|
||||
for i in range(3):
|
||||
print("USER LED at RTIO channel 0x{:06x}".format(len(self.rtio_channels)))
|
||||
phy = ttl_simple.Output(self.platform.request("user_led", i))
|
||||
self.submodules += phy
|
||||
self.rtio_channels.append(rtio.Channel.from_phy(phy))
|
||||
|
||||
self.config["HAS_RTIO_LOG"] = None
|
||||
self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
|
||||
self.rtio_channels.append(rtio.LogChannel())
|
||||
|
||||
self.add_rtio(self.rtio_channels, sed_lanes=description["sed_lanes"])
|
||||
|
||||
if has_grabber:
|
||||
self.config["HAS_GRABBER"] = None
|
||||
self.add_csr_group("grabber", self.grabber_csr_group)
|
||||
for grabber in self.grabber_csr_group:
|
||||
self.platform.add_false_path_constraints(
|
||||
self.crg.cd_sys.clk, getattr(self, grabber).deserializer.cd_cl.clk)
|
||||
|
||||
|
||||
class GenericMaster(MasterBase):
|
||||
def __init__(self, description, hw_rev=None, **kwargs):
|
||||
if hw_rev is None:
|
||||
hw_rev = description["hw_rev"]
|
||||
self.class_name_override = description["variant"]
|
||||
has_drtio_over_eem = any(peripheral["type"] == "shuttler" for peripheral in description["peripherals"])
|
||||
MasterBase.__init__(self,
|
||||
hw_rev=hw_rev,
|
||||
rtio_clk_freq=description["rtio_frequency"],
|
||||
enable_sata=description["enable_sata_drtio"],
|
||||
enable_sys5x=has_drtio_over_eem,
|
||||
**kwargs)
|
||||
if "ext_ref_frequency" in description:
|
||||
self.config["SI5324_EXT_REF"] = None
|
||||
self.config["EXT_REF_FREQUENCY"] = "{:.1f}".format(
|
||||
description["ext_ref_frequency"]/1e6)
|
||||
if hw_rev == "v1.0":
|
||||
# EEM clock fan-out from Si5324, not MMCX
|
||||
self.comb += self.platform.request("clk_sel").eq(1)
|
||||
|
||||
if has_drtio_over_eem:
|
||||
self.eem_drtio_channels = []
|
||||
has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"])
|
||||
if has_grabber:
|
||||
self.grabber_csr_group = []
|
||||
|
||||
self.rtio_channels = []
|
||||
eem_7series.add_peripherals(self, description["peripherals"])
|
||||
if hw_rev in ("v1.1", "v2.0"):
|
||||
for i in range(3):
|
||||
print("USER LED at RTIO channel 0x{:06x}".format(len(self.rtio_channels)))
|
||||
phy = ttl_simple.Output(self.platform.request("user_led", i))
|
||||
self.submodules += phy
|
||||
self.rtio_channels.append(rtio.Channel.from_phy(phy))
|
||||
|
||||
self.config["HAS_RTIO_LOG"] = None
|
||||
self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
|
||||
self.rtio_channels.append(rtio.LogChannel())
|
||||
|
||||
if has_drtio_over_eem:
|
||||
self.add_eem_drtio(self.eem_drtio_channels)
|
||||
self.add_drtio_cpuif_groups()
|
||||
|
||||
self.add_rtio(self.rtio_channels, sed_lanes=description["sed_lanes"])
|
||||
|
||||
if has_grabber:
|
||||
self.config["HAS_GRABBER"] = None
|
||||
self.add_csr_group("grabber", self.grabber_csr_group)
|
||||
for grabber in self.grabber_csr_group:
|
||||
self.platform.add_false_path_constraints(
|
||||
self.gt_drtio.gtps[0].txoutclk, getattr(self, grabber).deserializer.cd_cl.clk)
|
||||
|
||||
|
||||
class GenericSatellite(SatelliteBase):
|
||||
def __init__(self, description, hw_rev=None, **kwargs):
|
||||
if hw_rev is None:
|
||||
hw_rev = description["hw_rev"]
|
||||
self.class_name_override = description["variant"]
|
||||
SatelliteBase.__init__(self,
|
||||
hw_rev=hw_rev,
|
||||
rtio_clk_freq=description["rtio_frequency"],
|
||||
enable_sata=description["enable_sata_drtio"],
|
||||
**kwargs)
|
||||
if hw_rev == "v1.0":
|
||||
# EEM clock fan-out from Si5324, not MMCX
|
||||
self.comb += self.platform.request("clk_sel").eq(1)
|
||||
|
||||
has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"])
|
||||
if has_grabber:
|
||||
self.grabber_csr_group = []
|
||||
|
||||
self.rtio_channels = []
|
||||
eem_7series.add_peripherals(self, description["peripherals"])
|
||||
if hw_rev in ("v1.1", "v2.0"):
|
||||
for i in range(3):
|
||||
print("USER LED at RTIO channel 0x{:06x}".format(len(self.rtio_channels)))
|
||||
phy = ttl_simple.Output(self.platform.request("user_led", i))
|
||||
self.submodules += phy
|
||||
self.rtio_channels.append(rtio.Channel.from_phy(phy))
|
||||
|
||||
self.config["HAS_RTIO_LOG"] = None
|
||||
self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
|
||||
self.rtio_channels.append(rtio.LogChannel())
|
||||
|
||||
self.add_rtio(self.rtio_channels, sed_lanes=description["sed_lanes"])
|
||||
if has_grabber:
|
||||
self.config["HAS_GRABBER"] = None
|
||||
self.add_csr_group("grabber", self.grabber_csr_group)
|
||||
for grabber in self.grabber_csr_group:
|
||||
self.platform.add_false_path_constraints(
|
||||
self.gt_drtio.gtps[0].txoutclk, getattr(self, grabber).deserializer.cd_cl.clk)
|
||||
|
||||
|
||||
def main():
|
||||
parser = argparse.ArgumentParser(
|
||||
description="ARTIQ device binary builder for generic Kasli systems")
|
||||
builder_args(parser)
|
||||
soc_kasli_args(parser)
|
||||
parser.set_defaults(output_dir="artiq_kasli")
|
||||
parser.add_argument("description", metavar="DESCRIPTION",
|
||||
help="JSON system description file")
|
||||
parser.add_argument("--gateware-identifier-str", default=None,
|
||||
help="Override ROM identifier")
|
||||
args = parser.parse_args()
|
||||
description = jsondesc.load(args.description)
|
||||
|
||||
min_artiq_version = description["min_artiq_version"]
|
||||
if Version(artiq_version) < Version(min_artiq_version):
|
||||
logger.warning("ARTIQ version mismatch: current %s < %s minimum",
|
||||
artiq_version, min_artiq_version)
|
||||
|
||||
if description["target"] != "kasli":
|
||||
raise ValueError("Description is for a different target")
|
||||
|
||||
if description["drtio_role"] == "standalone":
|
||||
cls = GenericStandalone
|
||||
elif description["drtio_role"] == "master":
|
||||
cls = GenericMaster
|
||||
elif description["drtio_role"] == "satellite":
|
||||
cls = GenericSatellite
|
||||
else:
|
||||
raise ValueError("Invalid DRTIO role")
|
||||
|
||||
has_shuttler = any(peripheral["type"] == "shuttler" for peripheral in description["peripherals"])
|
||||
if has_shuttler and (description["drtio_role"] == "standalone"):
|
||||
raise ValueError("Shuttler requires DRTIO, please switch role to master")
|
||||
|
||||
soc = cls(description, gateware_identifier_str=args.gateware_identifier_str, **soc_kasli_argdict(args))
|
||||
args.variant = description["variant"]
|
||||
build_artiq_soc(soc, builder_argdict(args))
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
|
|
@ -16,7 +16,7 @@ ARTIQ itself does not depend on Nix, and it is also possible to compile everythi
|
|||
* Enable flakes in Nix by e.g. adding ``experimental-features = nix-command flakes`` to ``nix.conf`` (for example ``~/.config/nix/nix.conf``).
|
||||
* Clone the ARTIQ Git repository and run ``nix develop`` at the root (where ``flake.nix`` is).
|
||||
* Make the current source code of ARTIQ available to the Python interpreter by running ``export PYTHONPATH=`pwd`:$PYTHONPATH``.
|
||||
* You can then build the firmware and gateware with a command such as ``$ python -m artiq.gateware.targets.kasli``. If you are using a JSON system description file, use ``$ python -m artiq.gateware.targets.kasli_generic file.json``.
|
||||
* You can then build the firmware and gateware with a command such as ``$ python -m artiq.gateware.targets.kasli file.json``.
|
||||
* Flash the binaries into the FPGA board with a command such as ``$ artiq_flash --srcbuild -d artiq_kasli/<your_variant>``. You need to configure OpenOCD as explained :ref:`in the user section <configuring-openocd>`. OpenOCD is already part of the flake's development environment.
|
||||
* Check that the board boots and examine the UART messages by running a serial terminal program, e.g. ``$ flterm /dev/ttyUSB1`` (``flterm`` is part of MiSoC and installed in the flake's development environment). Leave the terminal running while you are flashing the board, so that you see the startup messages when the board boots immediately after flashing. You can also restart the board (without reflashing it) with ``$ artiq_flash start``.
|
||||
* The communication parameters are 115200 8-N-1. Ensure that your user has access to the serial device (e.g. by adding the user account to the ``dialout`` group).
|
||||
|
|
|
|||
Loading…
Reference in New Issue