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sayma_amc: cleanup (v2.0 only)

This commit is contained in:
Sebastien Bourdeauducq 2019-10-06 18:11:43 +08:00
parent e9b81f6e33
commit e6ff44301b
1 changed files with 5 additions and 5 deletions
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10
artiq/gateware/targets/sayma_amc.py
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@ -63,9 +63,10 @@ class SatelliteBase(BaseSoC):
# Use SFP0 to connect to master (Kasli) # Use SFP0 to connect to master (Kasli)
self.comb += platform.request("sfp_tx_disable", 0).eq(0) self.comb += platform.request("sfp_tx_disable", 0).eq(0)
drtio_data_pads = [platform.request("sfp", 0)] drtio_data_pads = [
if self.hw_rev == "v2.0": platform.request("sfp", 0),
drtio_data_pads.append(platform.request("rtm_amc_link")) platform.request("rtm_amc_link")
]
self.submodules.drtio_transceiver = gth_ultrascale.GTH( self.submodules.drtio_transceiver = gth_ultrascale.GTH(
clock_pads=platform.request("cdr_clk_clean"), clock_pads=platform.request("cdr_clk_clean"),
data_pads=drtio_data_pads, data_pads=drtio_data_pads,
@ -119,8 +120,7 @@ class SatelliteBase(BaseSoC):
self.add_csr_group("drtiorep", drtiorep_csr_group) self.add_csr_group("drtiorep", drtiorep_csr_group)
self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6) self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
if self.hw_rev == "v2.0": self.comb += platform.request("filtered_clk_sel").eq(1)
self.comb += platform.request("filtered_clk_sel").eq(1)
self.submodules.siphaser = SiPhaser7Series( self.submodules.siphaser = SiPhaser7Series(
si5324_clkin=platform.request("si5324_clkin"), si5324_clkin=platform.request("si5324_clkin"),
rx_synchronizer=self.rx_synchronizer, rx_synchronizer=self.rx_synchronizer,