From e664fe38b029a0cb425344be63a08d1cc4d98a68 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Wed, 20 Jan 2016 09:18:50 -0500 Subject: [PATCH] targets/kc705: fix DDS_RTIO_CLK_RATIO for AD9914. Closes #238 --- artiq/gateware/targets/kc705.py | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/artiq/gateware/targets/kc705.py b/artiq/gateware/targets/kc705.py index 71c069281..4503c2b73 100755 --- a/artiq/gateware/targets/kc705.py +++ b/artiq/gateware/targets/kc705.py @@ -133,8 +133,6 @@ class _NIST_QCx(MiniSoC, AMPSoC): self.submodules.rtio_crg = _RTIOCRG(self.platform, self.crg.cd_sys.clk) self.submodules.rtio = rtio.RTIO(rtio_channels) self.config["RTIO_FINE_TS_WIDTH"] = self.rtio.fine_ts_width - assert self.rtio.fine_ts_width <= 3 - self.config["DDS_RTIO_CLK_RATIO"] = 8 >> self.rtio.fine_ts_width self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) if isinstance(self.platform.toolchain, XilinxVivadoToolchain): @@ -198,6 +196,8 @@ class NIST_QC1(_NIST_QCx): rtio_channels.append(rtio.Channel.from_phy(phy)) self.config["RTIO_DDS_CHANNEL"] = len(rtio_channels) + assert self.rtio.fine_ts_width <= 3 + self.config["DDS_RTIO_CLK_RATIO"] = 8 >> self.rtio.fine_ts_width self.config["DDS_CHANNEL_COUNT"] = 8 self.config["DDS_AD9858"] = True phy = dds.AD9858(platform.request("dds"), 8) @@ -246,6 +246,8 @@ class NIST_QC2(_NIST_QCx): rtio_channels.append(rtio.Channel.from_phy(phy)) self.config["RTIO_DDS_CHANNEL"] = len(rtio_channels) + assert self.rtio.fine_ts_width <= 3 + self.config["DDS_RTIO_CLK_RATIO"] = 24 >> self.rtio.fine_ts_width self.config["DDS_CHANNEL_COUNT"] = 11 self.config["DDS_AD9914"] = True self.config["DDS_ONEHOT_SEL"] = True