From e624f453695483190ea61ce4049186e3f11d6640 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Tue, 10 Jan 2017 14:31:03 -0600 Subject: [PATCH] drtio: remove FIFO empty local detection optimization It optimizes a marginal case, it is difficult to get right (need to know the size of the FIFO for each channel), and it adds complexity and potential bug sources. --- artiq/gateware/drtio/rt_controller.py | 12 +++--------- artiq/test/gateware/drtio/test_full_stack.py | 15 +++++---------- 2 files changed, 8 insertions(+), 19 deletions(-) diff --git a/artiq/gateware/drtio/rt_controller.py b/artiq/gateware/drtio/rt_controller.py index ff58385ee..ffb8d96e5 100644 --- a/artiq/gateware/drtio/rt_controller.py +++ b/artiq/gateware/drtio/rt_controller.py @@ -139,8 +139,6 @@ class RTController(Module): cond_sequence_error = self.cri.o_timestamp < last_timestamps.dat_r cond_underflow = ((self.cri.o_timestamp[fine_ts_width:] - self.csrs.underflow_margin.storage[fine_ts_width:]) < self.counter.value_sys) - cond_fifo_emptied = ((last_timestamps.dat_r[fine_ts_width:] < self.counter.value_sys) - & (last_timestamps.dat_r != 0)) fsm.act("IDLE", If(self.cri.cmd == cri.commands["write"], @@ -161,13 +159,9 @@ class RTController(Module): rt_packets.write_stb.eq(1), If(rt_packets.write_ack, fifo_spaces.we.eq(1), - If(cond_fifo_emptied, - fifo_spaces.dat_w.eq(1), - ).Else( - fifo_spaces.dat_w.eq(fifo_spaces.dat_r - 1) - ), + fifo_spaces.dat_w.eq(fifo_spaces.dat_r - 1), last_timestamps.we.eq(1), - If(~cond_fifo_emptied & (fifo_spaces.dat_r <= 1), + If(fifo_spaces.dat_r <= 1, NextState("GET_FIFO_SPACE") ).Else( NextState("IDLE") @@ -189,7 +183,7 @@ class RTController(Module): fifo_spaces.we.eq(1), rt_packets.fifo_space_not_ack.eq(1), If(rt_packets.fifo_space_not, - If(rt_packets.fifo_space > 0, + If(rt_packets.fifo_space != 0, NextState("IDLE") ).Else( NextState("GET_FIFO_SPACE") diff --git a/artiq/test/gateware/drtio/test_full_stack.py b/artiq/test/gateware/drtio/test_full_stack.py index 1d758c5e8..a6af30daf 100644 --- a/artiq/test/gateware/drtio/test_full_stack.py +++ b/artiq/test/gateware/drtio/test_full_stack.py @@ -174,15 +174,6 @@ class TestFullStack(unittest.TestCase): # check that some writes caused FIFO space requests self.assertGreater(max_wlen, 5) - def test_fifo_emptied(): - # wait for all TTL events to execute - while len(ttl_changes) < len(correct_ttl_changes): - yield - # check "last timestamp passed" FIFO empty condition - delay(1000*8) - wlen = yield from write(0, 1) - self.assertEqual(wlen, 2) - def test_tsc_error(): err_present = yield from mgr.packet_err_present.read() self.assertEqual(err_present, 0) @@ -203,6 +194,10 @@ class TestFullStack(unittest.TestCase): err_present = yield from mgr.packet_err_present.read() self.assertEqual(err_present, 0) + def wait_ttl_events(): + while len(ttl_changes) < len(correct_ttl_changes): + yield + def test(): while not (yield from dut.master.link_layer.link_status.read()): yield @@ -213,8 +208,8 @@ class TestFullStack(unittest.TestCase): yield from test_sequence_error() yield from test_fifo_space() yield from test_large_data() - yield from test_fifo_emptied() yield from test_tsc_error() + yield from wait_ttl_events() @passive def check_ttls():