M-Labs/artiq
2
0
Fork 2
mirror of https://github.com/m-labs/artiq.git synced 2024-12-19 00:16:29 +08:00
Code Issues Projects Releases Wiki Activity

wrpll: add bit shift for collector helper output

Browse Source
This commit is contained in:
hartytp 2020-10-08 15:16:07 +08:00 committed by Sebastien Bourdeauducq
parent c9ae406ac6
commit e5e648bde1
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
artiq/gateware/drtio/wrpll/core.py
View File

@ -94,7 +94,7 @@ class WRPLL(Module, AutoCSR):
] ]
self.comb += [ self.comb += [
self.filter_helper.input.eq(self.collector.out_helper), self.filter_helper.input.eq(self.collector.out_helper << 22),
self.filter_helper.input_stb.eq(self.collector.out_stb), self.filter_helper.input_stb.eq(self.collector.out_stb),
self.filter_main.input.eq(self.collector.out_main), self.filter_main.input.eq(self.collector.out_main),
self.filter_main.input_stb.eq(self.collector.out_stb) self.filter_main.input_stb.eq(self.collector.out_stb)