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metlino,sayma: adapt to new EEM API 

This also enables 4X SERDES TTLs.
This commit is contained in:
Sebastien Bourdeauducq 2021-02-10 15:32:09 +08:00
parent 547254e89e
commit e54dd08821
2 changed files with 16 additions and 8 deletions
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15
artiq/gateware/targets/metlino.py
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@ -1,8 +1,10 @@
#!/usr/bin/env python3 #!/usr/bin/env python3
import argparse import argparse
from functools import partial
from migen import * from migen import *
from migen.build.generic_platform import IOStandard
from misoc.cores import gpio from misoc.cores import gpio
from misoc.integration.builder import builder_args, builder_argdict from misoc.integration.builder import builder_args, builder_argdict
@ -126,12 +128,13 @@ class Master(MiniSoC, AMPSoC):
self.submodules += phy self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy)) rtio_channels.append(rtio.Channel.from_phy(phy))
eem.DIO.add_std(self, 2, ttl_simple.Output, ttl_simple.Output, output_4x = partial(ttl_serdes_ultrascale.Output, 4)
iostandard="LVDS") eem.DIO.add_std(self, 2, output_4x, output_4x,
eem.Urukul.add_std(self, 0, 1, ttl_simple.Output, iostandard=lambda eem: IOStandard("LVDS"))
iostandard="LVDS") eem.Urukul.add_std(self, 0, 1, output_4x,
eem.Zotino.add_std(self, 3, ttl_simple.Output, iostandard=lambda eem: IOStandard("LVDS"))
iostandard="LVDS") eem.Zotino.add_std(self, 3, output_4x,
iostandard=lambda eem: IOStandard("LVDS"))
workaround_us_lvds_tristate(platform) workaround_us_lvds_tristate(platform)
self.config["HAS_RTIO_LOG"] = None self.config["HAS_RTIO_LOG"] = None

9
artiq/gateware/targets/sayma_amc.py
View File

@ -3,8 +3,10 @@
import argparse import argparse
import os import os
import warnings import warnings
from functools import partial
from migen import * from migen import *
from migen.build.generic_platform import IOStandard
from misoc.cores import gpio from misoc.cores import gpio
from misoc.integration.builder import builder_args, builder_argdict from misoc.integration.builder import builder_args, builder_argdict
@ -349,10 +351,13 @@ class Satellite(SatelliteBase):
# FMC-VHDCI-EEM DIOs x 2 (all OUTPUTs) # FMC-VHDCI-EEM DIOs x 2 (all OUTPUTs)
platform.add_connectors(fmcdio_vhdci_eem.connectors) platform.add_connectors(fmcdio_vhdci_eem.connectors)
output_4x = partial(ttl_serdes_ultrascale.Output, 4)
eem.DIO.add_std(self, 0, eem.DIO.add_std(self, 0,
ttl_simple.Output, ttl_simple.Output, iostandard="LVDS") output_4x, output_4x,
iostandard=lambda eem: IOStandard("LVDS"))
eem.DIO.add_std(self, 1, eem.DIO.add_std(self, 1,
ttl_simple.Output, ttl_simple.Output, iostandard="LVDS") output_4x, output_4x,
iostandard=lambda eem: IOStandard("LVDS"))
# FMC-DIO-32ch-LVDS-a Direction Control Pins (via shift register) as TTLs x 3 # FMC-DIO-32ch-LVDS-a Direction Control Pins (via shift register) as TTLs x 3
platform.add_extension(fmcdio_vhdci_eem.io) platform.add_extension(fmcdio_vhdci_eem.io)
print("fmcdio_vhdci_eem.[CLK, SER, LATCH] starting at RTIO channel 0x{:06x}" print("fmcdio_vhdci_eem.[CLK, SER, LATCH] starting at RTIO channel 0x{:06x}"