From e532261a9bb2e404807cdd1fd68e9640265921a9 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Wed, 23 Nov 2016 12:25:43 +0800 Subject: [PATCH] drtio: fix FullMemoryWE usage --- artiq/gateware/drtio/aux_controller.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/artiq/gateware/drtio/aux_controller.py b/artiq/gateware/drtio/aux_controller.py index 8755fedf2..e6b0879c9 100644 --- a/artiq/gateware/drtio/aux_controller.py +++ b/artiq/gateware/drtio/aux_controller.py @@ -205,14 +205,15 @@ class Receiver(Module, AutoCSR): ) +# TODO: FullMemoryWE should be applied by migen.build +@FullMemoryWE() class AuxController(Module): def __init__(self, link_layer): self.bus = wishbone.Interface() self.submodules.transmitter = Transmitter(link_layer, len(self.bus.dat_w)) self.submodules.receiver = Receiver(link_layer, len(self.bus.dat_w)) - # TODO: FullMemoryWE should be applied by migen.build - tx_sdram_if = FullMemoryWE()(wishbone.SRAM(self.transmitter.mem, read_only=False)) + tx_sdram_if = wishbone.SRAM(self.transmitter.mem, read_only=False) rx_sdram_if = wishbone.SRAM(self.receiver.mem, read_only=True) wsb = log2_int(len(self.bus.dat_w)//8) decoder = wishbone.Decoder(self.bus,