M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq.git
2
0
Fork 2
Code Issues Projects Releases Wiki Activity

firmware/liboard_artiq/ad9154.rs: add checks for jesd subclass 1 (verify that we receive the sysref and that phase error is within the specified window error threshold).

This commit is contained in:
Florent Kermarrec 2018-02-05 13:39:30 +01:00
parent 4c22d64ee4
commit e50bebb63d
1 changed files with 6 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
artiq/firmware/libboard_artiq/ad9154.rs
View File

@ -374,9 +374,15 @@ fn dac_setup(dacno: u8, linerate: u64) -> Result<(), &'static str> {
1*ad9154_reg::SYNCARM | 0*ad9154_reg::SYNCCLRSTKY | 1*ad9154_reg::SYNCARM | 0*ad9154_reg::SYNCCLRSTKY |
0*ad9154_reg::SYNCCLRLAST); 0*ad9154_reg::SYNCCLRLAST);
clock::spin_us(1000); // ensure at least one sysref edge clock::spin_us(1000); // ensure at least one sysref edge
if read(ad9154_reg::SYNC_CONTROL) & ad9154_reg::SYNCARM != 0 {
return Err("AD9154 no sysref edge");
}
if read(ad9154_reg::SYNC_STATUS) & ad9154_reg::SYNC_LOCK == 0 { if read(ad9154_reg::SYNC_STATUS) & ad9154_reg::SYNC_LOCK == 0 {
return Err("AD9154 no sync lock"); return Err("AD9154 no sync lock");
} }
if read(ad9154_reg::SYNC_STATUS) & ad9154_reg::SYNC_WLIM != 0 {
return Err("AD9154 sysref phase error");
}
write(ad9154_reg::XBAR_LN_0_1, write(ad9154_reg::XBAR_LN_0_1,
0*ad9154_reg::LOGICAL_LANE0_SRC | 1*ad9154_reg::LOGICAL_LANE1_SRC); 0*ad9154_reg::LOGICAL_LANE0_SRC | 1*ad9154_reg::LOGICAL_LANE1_SRC);
write(ad9154_reg::XBAR_LN_2_3, write(ad9154_reg::XBAR_LN_2_3,