mirror of
https://github.com/m-labs/artiq.git
synced 2024-12-28 20:53:35 +08:00
phaser: refactor coredevice driver
This commit is contained in:
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fdd2d6f2fb
commit
e505dfed5b
@ -93,12 +93,15 @@ class Phaser:
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def __init__(self, dmgr, channel_base, miso_delay=1, core_device="core"):
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self.channel_base = channel_base
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self.core = dmgr.get(core_device)
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# TODO: auto-align miso-delay in phy
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self.miso_delay = miso_delay
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# frame duration in mu (10 words, 8 clock cycles each 4 ns)
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# self.core.seconds_to_mu(10*8*4*ns) # unfortunately this returns 319
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assert self.core.ref_period == 1*ns
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self.t_frame = 10*8*4
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self.channel = [PhaserChannel(self, ch) for ch in range(2)]
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@kernel
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def init(self):
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"""Initialize the board.
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@ -150,17 +153,6 @@ class Phaser:
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delay(20*us) # slack
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return data
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@kernel
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def write16(self, addr, data: TInt32):
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"""Write 16 bit to a sequence of FPGA registers."""
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self.write8(addr, data >> 8)
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self.write8(addr + 1, data)
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@kernel
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def read16(self, addr) -> TInt32:
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"""Read 16 bit from a sequence of FPGA registers."""
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return (self.read8(addr) << 8) | self.read8(addr)
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@kernel
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def set_leds(self, leds):
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"""Set the front panel LEDs.
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@ -169,19 +161,32 @@ class Phaser:
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"""
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self.write8(PHASER_ADDR_LED, leds)
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@kernel
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def set_fan_mu(self, pwm):
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"""Set the fan duty cycle.
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:param pwm: Duty cycle (8 bit)
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"""
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self.write8(PHASER_ADDR_FAN, pwm)
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@kernel
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def set_fan(self, duty):
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"""Set the fan duty cycle.
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:param duty: Duty cycle (8 bit)
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:param duty: Duty cycle (0. to 1.)
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"""
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self.write8(PHASER_ADDR_FAN, duty)
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pwm = int32(round(duty*255.))
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if pwm < 0 or pwm > 0xff:
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raise ValueError("invalid duty cycle")
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self.set_fan_mu(pwm)
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@kernel
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def set_cfg(self, clk_sel=0, dac_resetb=1, dac_sleep=0, dac_txena=1,
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trf0_ps=0, trf1_ps=0, att0_rstn=1, att1_rstn=1):
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"""Set the configuration register.
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Each flag is a single bit (0 or 1).
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:param clk_sel: Select the external SMA clock input
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:param dac_resetb: Active low DAC reset pin
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:param dac_sleep: DAC sleep pin
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@ -192,9 +197,10 @@ class Phaser:
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:param att1_rstn: Active low attenuator 1 reset
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"""
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self.write8(PHASER_ADDR_CFG,
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(clk_sel << 0) | (dac_resetb << 1) | (dac_sleep << 2) |
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(dac_txena << 3) | (trf0_ps << 4) | (trf1_ps << 5) |
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(att0_rstn << 6) | (att1_rstn << 7))
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((clk_sel & 1) << 0) | ((dac_resetb & 1) << 1) |
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((dac_sleep & 1) << 2) | ((dac_txena & 1) << 3) |
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((trf0_ps & 1) << 4) | ((trf1_ps & 1) << 5) |
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((att0_rstn & 1) << 6) | ((att1_rstn & 1) << 7))
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@kernel
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def get_sta(self):
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@ -216,93 +222,13 @@ class Phaser:
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@kernel
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def get_crc_err(self):
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"""Get the frame CRC error counter."""
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"""Get the frame CRC error counter.
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:return: The number of frames with CRC mismatches sind the reset of the
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device. Overflows at 256.
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"""
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return self.read8(PHASER_ADDR_CRC_ERR)
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@kernel
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def get_dac_data(self, ch) -> TInt32:
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"""Get a sample of the current DAC data.
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The data is split accross multiple registers and thus the data
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is only valid if constant.
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:param ch: DAC channel pair (0 or 1)
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:return: DAC data as 32 bit IQ
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"""
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data = 0
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for addr in range(4):
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data <<= 8
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data |= self.read8(PHASER_ADDR_DAC0_DATA + (ch << 4) + addr)
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delay(20*us) # slack
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return data
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@kernel
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def set_dac_test(self, ch, data: TInt32):
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"""Set the DAC test data.
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:param ch: DAC channel pair (0 or 1)
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:param data: 32 bit IQ test data
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"""
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for addr in range(4):
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byte = data >> 24
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self.write8(PHASER_ADDR_DAC0_TEST + (ch << 4) + addr, byte)
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data <<= 8
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@kernel
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def set_duc_cfg(self, ch, clr=0, clr_once=0, select=0):
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"""Set the digital upconverter and interpolator configuration.
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:param ch: DAC channel pair (0 or 1)
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:param clr: Keep the phase accumulator cleared
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:param clr_once: Clear the phase accumulator for one cycle
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:param select: Select the data to send to the DAC (0: DUC data, 1: test
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data)
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"""
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self.write8(PHASER_ADDR_DUC0_CFG + (ch << 4),
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(clr << 0) | (clr_once << 1) | (select << 2))
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@kernel
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def set_duc_frequency_mu(self, ch, ftw):
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"""Set the DUC frequency.
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:param ch: DAC channel pair (0 or 1)
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:param ftw: DUC frequency tuning word
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"""
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self.write32(PHASER_ADDR_DUC0_F + (ch << 4), ftw)
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@kernel
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def set_duc_frequency(self, ch, frequency):
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"""Set the DUC frequency.
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:param ch: DAC channel pair (0 or 1)
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:param frequency: DUC frequency in Hz
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"""
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if ch < 0 or ch > 1:
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raise ValueError("invalid channel index")
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ftw = int32(round(frequency*((1 << 32)/500e6)))
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self.set_duc_frequency_mu(ch, ftw)
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@kernel
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def set_duc_phase_mu(self, ch, pow):
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"""Set the DUC phase offset
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:param ch: DAC channel pair (0 or 1)
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:param pow: DUC phase offset word
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"""
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self.write16(PHASER_ADDR_DUC0_P + (ch << 4), pow)
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@kernel
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def set_duc_phase(self, ch, phase):
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"""Set the DUC phase.
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:param ch: DAC channel pair (0 or 1)
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:param phase: DUC phase in turns
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"""
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if ch < 0 or ch > 1:
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raise ValueError("invalid channel index")
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pow = int32(round(phase*(1 << 16))) & 0xffff
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self.set_duc_phase_mu(ch, pow)
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@kernel
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def duc_stb(self):
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"""Strobe the DUC configuration register update.
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@ -389,50 +315,141 @@ class Phaser:
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data |= self.spi_read()
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return data
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class PhaserChannel:
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"""Phaser channel IQ pair"""
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kernel_invariants = {"channel", "phaser"}
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def __init__(self, phaser, channel):
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self.phaser = phaser
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self.channel = channel
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self.oscillator = [PhaserOscillator(self, osc) for osc in range(5)]
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@kernel
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def att_write(self, ch, data):
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def get_dac_data(self) -> TInt32:
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"""Get a sample of the current DAC data.
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The data is split accross multiple registers and thus the data
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is only valid if constant.
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:return: DAC data as 32 bit IQ. I in the 16 LSB, Q in the 16 MSB
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"""
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return self.phaser.read32(PHASER_ADDR_DAC0_DATA + (self.channel << 4))
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@kernel
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def set_dac_test(self, data: TInt32):
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"""Set the DAC test data.
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:param data: 32 bit IQ test data, I in the 16 LSB, Q in the 16 MSB
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"""
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self.phaser.write32(PHASER_ADDR_DAC0_TEST + (self.channel << 4), data)
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@kernel
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def set_duc_cfg(self, clr=0, clr_once=0, select=0):
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"""Set the digital upconverter and interpolator configuration.
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:param clr: Keep the phase accumulator cleared
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:param clr_once: Clear the phase accumulator for one cycle
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:param select: Select the data to send to the DAC (0: DUC data, 1: test
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data)
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"""
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if select < 0 or select > 3:
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raise ValueError("invalid data select")
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self.phaser.write8(PHASER_ADDR_DUC0_CFG + (self.channel << 4),
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((clr & 1) << 0) | ((clr_once & 1) << 1) |
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((select & 3) << 2))
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@kernel
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def set_duc_frequency_mu(self, ftw):
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"""Set the DUC frequency.
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:param ftw: DUC frequency tuning word
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"""
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self.phaser.write32(PHASER_ADDR_DUC0_F + (self.channel << 4), ftw)
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@kernel
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def set_duc_frequency(self, frequency):
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"""Set the DUC frequency.
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:param frequency: DUC frequency in Hz
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"""
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ftw = int32(round(frequency*((1 << 32)/500e6)))
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self.set_duc_frequency_mu(ftw)
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@kernel
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def set_duc_phase_mu(self, pow):
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"""Set the DUC phase offset
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:param pow: DUC phase offset word
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"""
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addr = PHASER_ADDR_DUC0_P + (self.channel << 4)
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self.phaser.write8(addr, pow >> 8)
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self.phaser.write8(addr + 1, pow)
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@kernel
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def set_duc_phase(self, phase):
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"""Set the DUC phase.
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:param phase: DUC phase in turns
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"""
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pow = int32(round(phase*(1 << 16)))
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self.set_duc_phase_mu(pow)
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@kernel
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def set_att_mu(self, data):
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"""Set channel attenuation.
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:param ch: RF channel (0 or 1)
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:param data: Attenuator data
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"""
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div = 34 # 30 ns min period
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t_xfer = self.core.seconds_to_mu((8 + 1)*div*4*ns)
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self.spi_cfg(select=PHASER_SEL_ATT0 << ch, div=div, end=1)
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self.spi_write(data)
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t_xfer = self.phaser.core.seconds_to_mu((8 + 1)*div*4*ns)
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self.phaser.spi_cfg(select=PHASER_SEL_ATT0 << self.channel, div=div,
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end=1)
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self.phaser.spi_write(data)
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delay_mu(t_xfer)
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@kernel
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def att_read(self, ch) -> TInt32:
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def set_att(self, att):
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"""Set channel attenuation in SI units.
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:param att: Attenuation in dB
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"""
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data = 0xff - int32(round(att*8))
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if data < 0 or data > 0xff:
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raise ValueError("invalid attenuation")
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self.set_att_mu(data)
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@kernel
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def get_att_mu(self) -> TInt32:
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"""Read current attenuation.
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The current attenuation value is read without side effects.
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:param ch: RF channel (0 or 1)
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:return: Current attenuation
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"""
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div = 34
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t_xfer = self.core.seconds_to_mu((8 + 1)*div*4*ns)
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self.spi_cfg(select=PHASER_SEL_ATT0 << ch, div=div, end=0)
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self.spi_write(0)
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t_xfer = self.phaser.core.seconds_to_mu((8 + 1)*div*4*ns)
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self.phaser.spi_cfg(select=PHASER_SEL_ATT0 << self.channel, div=div,
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end=0)
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self.phaser.spi_write(0)
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delay_mu(t_xfer)
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data = self.spi_read()
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data = self.phaser.spi_read()
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delay(10*us) # slack
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self.spi_cfg(select=PHASER_SEL_ATT0 << ch, div=div, end=1)
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self.spi_write(data)
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self.phaser.spi_cfg(select=PHASER_SEL_ATT0 << self.channel, div=div,
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end=1)
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self.phaser.spi_write(data)
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delay_mu(t_xfer)
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return data
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@kernel
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def trf_write(self, ch, data, readback=False):
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def trf_write(self, data, readback=False):
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"""Write 32 bits to a TRF upconverter.
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:param ch: RF channel (0 or 1)
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:param data: Register data (32 bit)
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:param data: Register data (32 bit) containing encoded address
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:param readback: Whether to return the read back MISO data
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"""
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div = 34 # 50 ns min period
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t_xfer = self.core.seconds_to_mu((8 + 1)*div*4*ns)
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t_xfer = self.phaser.core.seconds_to_mu((8 + 1)*div*4*ns)
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read = 0
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end = 0
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clk_phase = 0
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@ -442,91 +459,82 @@ class Phaser:
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if i == 0 or i == 3:
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if i == 3:
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end = 1
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self.spi_cfg(select=PHASER_SEL_TRF0 << ch, div=div,
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lsb_first=1, clk_phase=clk_phase, end=end)
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self.spi_write(data)
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self.phaser.spi_cfg(select=PHASER_SEL_TRF0 << self.channel,
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div=div, lsb_first=1, clk_phase=clk_phase,
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end=end)
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self.phaser.spi_write(data)
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data >>= 8
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delay_mu(t_xfer)
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if readback:
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read >>= 8
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read |= self.spi_read() << 24
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read |= self.phaser.spi_read() << 24
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delay(10*us) # slack
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return read
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@kernel
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def trf_read(self, ch, addr, cnt_mux_sel=0) -> TInt32:
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def trf_read(self, addr, cnt_mux_sel=0) -> TInt32:
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"""TRF upconverter register read.
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:param ch: RF channel (0 or 1)
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:param addr: Register address to read
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:param addr: Register address to read (0 to 7)
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:param cnt_mux_sel: Report VCO counter min frequency
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or max frequency
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:return: Register data (32 bit)
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"""
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self.trf_write(ch, 0x80000008 | (addr << 28) | (cnt_mux_sel << 27))
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self.trf_write(0x80000008 | (addr << 28) | (cnt_mux_sel << 27))
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# single clk pulse with ~LE to start readback
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self.spi_cfg(select=0, div=34, end=1, length=1)
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self.spi_write(0)
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self.phaser.spi_cfg(select=0, div=34, end=1, length=1)
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self.phaser.spi_write(0)
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delay((1 + 1)*32*4*ns)
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return self.trf_write(ch, 0x00000008, readback=True)
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return self.trf_write(0x00000008, readback=True)
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class PhaserOscillator:
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"""Phaser IQ channel oscillator"""
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kernel_invariants = {"channel", "base_addr"}
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def __init__(self, channel, oscillator):
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self.channel = channel
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self.base_addr = ((self.channel.phaser.channel_base + 1 +
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self.channel.channel) << 8) | (oscillator << 1)
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@kernel
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def set_frequency_mu(self, ch, osc, ftw):
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def set_frequency_mu(self, ftw):
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"""Set Phaser MultiDDS frequency tuning word.
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:param ch: RF channel (0 or 1)
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:param osc: Oscillator number (0 to 4)
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:param ftw: Frequency tuning word (32 bit)
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"""
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addr = ((self.channel_base + 1 + ch) << 8) | (osc << 1)
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rtio_output(addr, ftw)
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rtio_output(self.base_addr, ftw)
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@kernel
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def set_frequency(self, ch, osc, frequency):
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def set_frequency(self, frequency):
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"""Set Phaser MultiDDS frequency.
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:param ch: RF channel (0 or 1)
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:param osc: Oscillator number (0 to 4)
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:param frequency: Frequency in Hz
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"""
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if ch < 0 or ch > 1:
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raise ValueError("invalid channel index")
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if osc < 0 or osc > 4:
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raise ValueError("invalid oscillator index")
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ftw = int32(round(frequency*((1 << 32)/125e6)))
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self.set_frequency_mu(ch, osc, ftw)
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self.set_frequency_mu(ftw)
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@kernel
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def set_amplitude_phase_mu(self, ch, osc, asf=0x7fff, pow=0, clr=0):
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def set_amplitude_phase_mu(self, asf=0x7fff, pow=0, clr=0):
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"""Set Phaser MultiDDS amplitude, phase offset and accumulator clear.
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:param ch: RF channel (0 or 1)
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:param osc: Oscillator number (0 to 4)
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:param asf: Amplitude (15 bit)
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:param pow: Phase offset word (16 bit)
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:param clr: Clear the phase accumulator (persistent)
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"""
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addr = ((self.channel_base + 1 + ch) << 8) | (osc << 1) | 1
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data = (asf & 0x7fff) | ((clr & 1) << 15) | ((pow & 0xffff) << 16)
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rtio_output(addr, data)
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data = (asf & 0x7fff) | ((clr & 1) << 15) | (pow << 16)
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rtio_output(self.base_addr | 1, data)
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@kernel
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def set_amplitude_phase(self, ch, osc, amplitude, phase=0., clr=0):
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def set_amplitude_phase(self, amplitude, phase=0., clr=0):
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||||
"""Set Phaser MultiDDS amplitude and phase.
|
||||
|
||||
:param ch: RF channel (0 or 1)
|
||||
:param osc: Oscillator number (0 to 4)
|
||||
:param amplitude: Amplitude in units of full scale
|
||||
:param phase: Phase in turns
|
||||
:param clr: Clear the phase accumulator (persistent)
|
||||
"""
|
||||
if ch < 0 or ch > 1:
|
||||
raise ValueError("invalid channel index")
|
||||
if osc < 0 or osc > 4:
|
||||
raise ValueError("invalid oscillator index")
|
||||
asf = int32(round(amplitude*0x7fff))
|
||||
if asf < 0 or asf > 0x7fff:
|
||||
raise ValueError("invalid amplitude")
|
||||
pow = int32(round(phase*(1 << 16)))
|
||||
self.set_amplitude_phase_mu(ch, osc, asf, pow, clr)
|
||||
self.set_amplitude_phase_mu(asf, pow, clr)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user