mirror of https://github.com/m-labs/artiq.git
coredevice/adf5356: port to NAC3
This commit is contained in:
parent
519e3d64d8
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e45c194c49
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@ -8,25 +8,36 @@ on Mirny-style prefixed SPI buses.
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# https://www.analog.com/media/en/technical-documentation/data-sheets/ADF5355.pdf
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# https://www.analog.com/media/en/technical-documentation/user-guides/EV-ADF5355SD1Z-UG-1087.pdf
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from numpy import int32, int64
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# NAC3TODO from math import floor, ceil
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from artiq.language.core import kernel, portable, delay
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from artiq.language.core import nac3, KernelInvariant, kernel, portable, round64
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from artiq.language.units import us, GHz, MHz
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from artiq.language.types import TInt32, TInt64
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from artiq.coredevice import spi2 as spi
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from artiq.coredevice.core import Core
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from artiq.coredevice.mirny import Mirny
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from artiq.coredevice.ttl import TTLOut
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from artiq.coredevice.spi2 import *
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from artiq.coredevice.adf5356_reg import *
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from numpy import int32, int64, floor, ceil
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# NAC3TODO
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@portable
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def floor(x: float) -> int32:
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return 0
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@portable
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def ceil(x: float) -> int32:
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return 0
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#
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SPI_CONFIG = (
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0 * spi.SPI_OFFLINE
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| 0 * spi.SPI_END
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| 0 * spi.SPI_INPUT
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| 1 * spi.SPI_CS_POLARITY
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| 0 * spi.SPI_CLK_POLARITY
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| 0 * spi.SPI_CLK_PHASE
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| 0 * spi.SPI_LSB_FIRST
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| 0 * spi.SPI_HALF_DUPLEX
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0 * SPI_OFFLINE
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| 0 * SPI_END
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| 0 * SPI_INPUT
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| 1 * SPI_CS_POLARITY
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| 0 * SPI_CLK_POLARITY
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| 0 * SPI_CLK_PHASE
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| 0 * SPI_LSB_FIRST
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| 0 * SPI_HALF_DUPLEX
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)
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@ -38,6 +49,7 @@ ADF5356_MAX_MODULUS2 = int32(1 << 28) # FIXME: ADF5356 has 28 bits MOD2
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ADF5356_MAX_R_CNT = int32(1023)
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@nac3
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class ADF5356:
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"""Analog Devices AD[45]35[56] family of GHz PLLs.
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@ -49,7 +61,14 @@ class ADF5356:
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:param core_device: Core device name (default: "core")
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"""
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kernel_invariants = {"cpld", "sw", "channel", "core", "sysclk"}
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core: KernelInvariant[Core]
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cpld: KernelInvariant[Mirny]
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channel: KernelInvariant[int32]
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sw: KernelInvariant[TTLOut]
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sysclk: KernelInvariant[float]
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regs: list[int32]
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ref_doubler: bool
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ref_divider: bool
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def __init__(
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self,
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@ -74,7 +93,7 @@ class ADF5356:
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self._init_registers()
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@kernel
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def init(self, blind=False):
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def init(self, blind: bool = False):
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"""
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Initialize and configure the PLL.
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@ -84,18 +103,20 @@ class ADF5356:
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# MUXOUT = VDD
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self.regs[4] = ADF5356_REG4_MUXOUT_UPDATE(self.regs[4], 1)
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self.sync()
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delay(1000 * us)
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self.core.delay(1000. * us)
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if not self.read_muxout():
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raise ValueError("MUXOUT not high")
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delay(800 * us)
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# NAC3TODO raise ValueError("MUXOUT not high")
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pass
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self.core.delay(800. * us)
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# MUXOUT = DGND
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self.regs[4] = ADF5356_REG4_MUXOUT_UPDATE(self.regs[4], 2)
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self.sync()
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delay(1000 * us)
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self.core.delay(1000. * us)
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if self.read_muxout():
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raise ValueError("MUXOUT not low")
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delay(800 * us)
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# NAC3TODO raise ValueError("MUXOUT not low")
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pass
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self.core.delay(800. * us)
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# MUXOUT = digital lock-detect
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self.regs[4] = ADF5356_REG4_MUXOUT_UPDATE(self.regs[4], 6)
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@ -103,7 +124,7 @@ class ADF5356:
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self.sync()
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@kernel
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def set_att_mu(self, att):
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def set_att_mu(self, att: int32):
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"""Set digital step attenuator in machine units.
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:param att: Attenuation setting, 8 bit digital.
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@ -111,11 +132,11 @@ class ADF5356:
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self.cpld.set_att_mu(self.channel, att)
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@kernel
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def write(self, data):
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def write(self, data: int32):
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self.cpld.write_ext(self.channel | 4, 32, data)
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@kernel
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def read_muxout(self):
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def read_muxout(self) -> bool:
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"""
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Read the state of the MUXOUT line.
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@ -124,7 +145,7 @@ class ADF5356:
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return bool(self.cpld.read_reg(0) & (1 << (self.channel + 8)))
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@kernel
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def set_output_power_mu(self, n):
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def set_output_power_mu(self, n: int32):
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"""
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Set the power level at output A of the PLL chip in machine units.
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@ -132,13 +153,14 @@ class ADF5356:
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:param n: output power setting, 0, 1, 2, or 3 (see ADF5356 datasheet, fig. 44).
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"""
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if n not in [0, 1, 2, 3]:
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raise ValueError("invalid power setting")
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if not 0 <= n <= 3:
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# NAC3TODO raise ValueError("invalid power setting")
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pass
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self.regs[6] = ADF5356_REG6_RF_OUTPUT_A_POWER_UPDATE(self.regs[6], n)
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self.sync()
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@portable
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def output_power_mu(self):
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def output_power_mu(self) -> int32:
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"""
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Return the power level at output A of the PLL chip in machine units.
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"""
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@ -161,25 +183,27 @@ class ADF5356:
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self.sync()
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@kernel
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def set_frequency(self, f):
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def set_frequency(self, f: float):
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"""
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Output given frequency on output A.
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:param f: 53.125 MHz <= f <= 6800 MHz
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"""
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freq = int64(round(f))
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freq = round64(f)
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if freq > ADF5356_MAX_VCO_FREQ:
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raise ValueError("Requested too high frequency")
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# NAC3TODO raise ValueError("Requested too high frequency")
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pass
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# select minimal output divider
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rf_div_sel = 0
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while freq < ADF5356_MIN_VCO_FREQ:
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freq <<= 1
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freq <<= int64(1)
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rf_div_sel += 1
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if (1 << rf_div_sel) > 64:
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raise ValueError("Requested too low frequency")
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# NAC3TODO raise ValueError("Requested too low frequency")
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pass
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# choose reference divider that maximizes PFD frequency
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self.regs[4] = ADF5356_REG4_R_COUNTER_UPDATE(
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@ -193,7 +217,7 @@ class ADF5356:
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n_min, n_max = 75, 65535
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# adjust reference divider to be able to match n_min constraint
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while n_min * f_pfd > freq:
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while int64(n_min) * f_pfd > freq:
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r = ADF5356_REG4_R_COUNTER_GET(self.regs[4])
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self.regs[4] = ADF5356_REG4_R_COUNTER_UPDATE(self.regs[4], r + 1)
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f_pfd = self.f_pfd()
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@ -207,7 +231,8 @@ class ADF5356:
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)
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if not (n_min <= n <= n_max):
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raise ValueError("Invalid INT value")
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# NAC3TODO raise ValueError("Invalid INT value")
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pass
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# configure PLL
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self.regs[0] = ADF5356_REG0_INT_VALUE_UPDATE(self.regs[0], n)
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@ -221,10 +246,10 @@ class ADF5356:
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self.regs[6] = ADF5356_REG6_RF_DIVIDER_SELECT_UPDATE(self.regs[6], rf_div_sel)
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self.regs[6] = ADF5356_REG6_CP_BLEED_CURRENT_UPDATE(
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self.regs[6], int32(floor(24 * f_pfd / (61.44 * MHz)))
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self.regs[6], floor(24. * float(f_pfd) / (61.44 * MHz))
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)
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self.regs[9] = ADF5356_REG9_VCO_BAND_DIVISION_UPDATE(
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self.regs[9], int32(ceil(f_pfd / 160e3))
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self.regs[9], ceil(float(f_pfd) / 160e3)
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)
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# commit
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@ -236,21 +261,21 @@ class ADF5356:
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Write all registers to the device. Attempts to lock the PLL.
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"""
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f_pfd = self.f_pfd()
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delay(200 * us) # Slack
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self.core.delay(200. * us) # Slack
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if f_pfd <= 75.0 * MHz:
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if f_pfd <= round64(75.0 * MHz):
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for i in range(13, 0, -1):
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self.write(self.regs[i])
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delay(200 * us)
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self.core.delay(200. * us)
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self.write(self.regs[0] | ADF5356_REG0_AUTOCAL(1))
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else:
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# AUTOCAL AT HALF PFD FREQUENCY
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# calculate PLL at f_pfd/2
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n, frac1, (frac2_msb, frac2_lsb), (mod2_msb, mod2_lsb) = calculate_pll(
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self.f_vco(), f_pfd >> 1
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self.f_vco(), f_pfd >> int64(1)
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)
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delay(200 * us) # Slack
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self.core.delay(200. * us) # Slack
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self.write(
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13
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@ -273,7 +298,7 @@ class ADF5356:
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)
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self.write(1 | ADF5356_REG1_MAIN_FRAC_VALUE(frac1))
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delay(200 * us)
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self.core.delay(200. * us)
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self.write(ADF5356_REG0_INT_VALUE(n) | ADF5356_REG0_AUTOCAL(1))
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# RELOCK AT WANTED PFD FREQUENCY
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@ -285,7 +310,7 @@ class ADF5356:
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self.write(self.regs[0] & ~ADF5356_REG0_AUTOCAL(1))
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@portable
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def f_pfd(self) -> TInt64:
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def f_pfd(self) -> int64:
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"""
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Return the PFD frequency for the cached set of registers.
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"""
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@ -295,35 +320,35 @@ class ADF5356:
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return self._compute_pfd_frequency(r, d, t)
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@portable
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def f_vco(self) -> TInt64:
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def f_vco(self) -> int64:
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"""
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Return the VCO frequency for the cached set of registers.
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"""
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return int64(
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self.f_pfd()
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return round64(
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float(self.f_pfd())
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* (
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self.pll_n()
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+ (self.pll_frac1() + self.pll_frac2() / self.pll_mod2())
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/ ADF5356_MODULUS1
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)
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float(self.pll_n())
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+ (float(self.pll_frac1() + self.pll_frac2()) / float(self.pll_mod2()))
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/ float(ADF5356_MODULUS1)
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)
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)
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@portable
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def pll_n(self) -> TInt32:
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def pll_n(self) -> int32:
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"""
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Return the PLL integer value (INT) for the cached set of registers.
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"""
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return ADF5356_REG0_INT_VALUE_GET(self.regs[0])
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@portable
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def pll_frac1(self) -> TInt32:
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def pll_frac1(self) -> int32:
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"""
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Return the main fractional value (FRAC1) for the cached set of registers.
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"""
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return ADF5356_REG1_MAIN_FRAC_VALUE_GET(self.regs[1])
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@portable
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def pll_frac2(self) -> TInt32:
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def pll_frac2(self) -> int32:
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"""
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Return the auxiliary fractional value (FRAC2) for the cached set of registers.
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"""
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@ -332,7 +357,7 @@ class ADF5356:
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) | ADF5356_REG2_AUX_FRAC_LSB_VALUE_GET(self.regs[2])
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@portable
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def pll_mod2(self) -> TInt32:
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def pll_mod2(self) -> int32:
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"""
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Return the auxiliary modulus value (MOD2) for the cached set of registers.
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"""
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@ -341,14 +366,14 @@ class ADF5356:
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) | ADF5356_REG2_AUX_MOD_LSB_VALUE_GET(self.regs[2])
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@portable
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def ref_counter(self) -> TInt32:
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def ref_counter(self) -> int32:
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"""
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Return the reference counter value (R) for the cached set of registers.
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"""
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return ADF5356_REG4_R_COUNTER_GET(self.regs[4])
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@portable
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def output_divider(self) -> TInt32:
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def output_divider(self) -> int32:
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"""
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Return the value of the output A divider.
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"""
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@ -398,7 +423,7 @@ class ADF5356:
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# single-ended reference mode is recommended
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# for references up to 250 MHz, even if the signal is differential
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if self.sysclk <= 250 * MHz:
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if self.sysclk <= 250.*MHz:
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self.regs[4] |= ADF5356_REG4_REF_MODE(0)
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else:
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self.regs[4] |= ADF5356_REG4_REF_MODE(1)
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@ -440,7 +465,7 @@ class ADF5356:
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# charge pump bleed current
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self.regs[6] |= ADF5356_REG6_CP_BLEED_CURRENT(
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int32(floor(24 * self.f_pfd() / (61.44 * MHz)))
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floor(24. * float(self.f_pfd()) / (61.44 * MHz))
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)
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# direct feedback from VCO to N counter
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@ -484,7 +509,7 @@ class ADF5356:
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)
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self.regs[9] |= ADF5356_REG9_VCO_BAND_DIVISION(
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int32(ceil(self.f_pfd() / 160e3))
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ceil(float(self.f_pfd()) / 160e3)
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)
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# REG10
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@ -513,39 +538,39 @@ class ADF5356:
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self.regs[12] = int32(0x15FC)
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@portable
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def _compute_pfd_frequency(self, r, d, t) -> TInt64:
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def _compute_pfd_frequency(self, r: int32, d: int32, t: int32) -> int64:
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"""
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Calculate the PFD frequency from the given reference path parameters
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"""
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return int64(self.sysclk * ((1 + d) / (r * (1 + t))))
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return round64(self.sysclk * (float(1 + d) / float(r * (1 + t))))
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@portable
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def _compute_reference_counter(self) -> TInt32:
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def _compute_reference_counter(self) -> int32:
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"""
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Determine the reference counter R that maximizes the PFD frequency
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"""
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d = ADF5356_REG4_R_DOUBLER_GET(self.regs[4])
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t = ADF5356_REG4_R_DIVIDER_GET(self.regs[4])
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r = 1
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while self._compute_pfd_frequency(r, d, t) > ADF5356_MAX_FREQ_PFD:
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while self._compute_pfd_frequency(r, d, t) > int64(ADF5356_MAX_FREQ_PFD):
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r += 1
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return int32(r)
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return r
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@portable
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def gcd(a, b):
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while b:
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def gcd(a: int64, b: int64) -> int64:
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while b != int64(0):
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a, b = b, a % b
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return a
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@portable
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def split_msb_lsb_28b(v):
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return int32((v >> 14) & 0x3FFF), int32(v & 0x3FFF)
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def split_msb_lsb_28b(v: int32) -> tuple[int32, int32]:
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return (v >> 14) & 0x3FFF, v & 0x3FFF
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@portable
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def calculate_pll(f_vco: TInt64, f_pfd: TInt64):
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def calculate_pll(f_vco: int64, f_pfd: int64) -> tuple[int32, int32, tuple[int32, int32], tuple[int32, int32]]:
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"""
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Calculate fractional-N PLL parameters such that
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@ -558,25 +583,23 @@ def calculate_pll(f_vco: TInt64, f_pfd: TInt64):
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:param f_pfd: PFD frequency
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:return: ``(n, frac1, (frac2_msb, frac2_lsb), (mod2_msb, mod2_lsb))``
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"""
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f_pfd = int64(f_pfd)
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f_vco = int64(f_vco)
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# integral part
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n, r = int32(f_vco // f_pfd), f_vco % f_pfd
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# main fractional part
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r *= ADF5356_MODULUS1
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r *= int64(ADF5356_MODULUS1)
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frac1, frac2 = int32(r // f_pfd), r % f_pfd
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# auxiliary fractional part
|
||||
mod2 = f_pfd
|
||||
|
||||
while mod2 > ADF5356_MAX_MODULUS2:
|
||||
mod2 >>= 1
|
||||
frac2 >>= 1
|
||||
while mod2 > int64(ADF5356_MAX_MODULUS2):
|
||||
mod2 >>= int64(1)
|
||||
frac2 >>= int64(1)
|
||||
|
||||
gcd_div = gcd(frac2, mod2)
|
||||
mod2 //= gcd_div
|
||||
frac2 //= gcd_div
|
||||
|
||||
return n, frac1, split_msb_lsb_28b(frac2), split_msb_lsb_28b(mod2)
|
||||
return n, frac1, split_msb_lsb_28b(int32(frac2)), split_msb_lsb_28b(int32(mod2))
|
||||
|
|
|
|||
Loading…
Reference in New Issue