From e400f8d672d23e621eea14986281315278544a50 Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Fri, 14 Oct 2016 09:54:56 +0200 Subject: [PATCH] phaser: add two more registers before jesd --- artiq/gateware/targets/kc705.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/artiq/gateware/targets/kc705.py b/artiq/gateware/targets/kc705.py index b593869e1..6d7dedc01 100755 --- a/artiq/gateware/targets/kc705.py +++ b/artiq/gateware/targets/kc705.py @@ -511,10 +511,11 @@ class AD9154(Module, AutoCSR): x = Signal() y = Signal() - self.sync.jesd += x.eq(~x) + z = Signal() + self.sync.jesd += x.eq(~x), z.eq(x == y) self.sync.rio_phy += y.eq(x) for conv, ch in zip(self.jesd.core.sink.flatten(), self.sawgs): - self.comb += conv.eq(Mux(x != y, Cat(ch.o[:2]), Cat(ch.o[2:]))) + self.sync.jesd += conv.eq(Mux(z, Cat(ch.o[:2]), Cat(ch.o[2:]))) class Phaser(_NIST_Ions):