ttl_simple: support differential io

artiq/gateware/rtio/phy/ttl_simple.py

@@ -1,13 +1,15 @@
 from migen import *
 from migen.genlib.cdc import MultiReg
+from migen.genlib.io import DifferentialInput, DifferentialOutput
 
 from artiq.gateware.rtio import rtlink
 
 
 class Output(Module):
-    def __init__(self, pad):
+    def __init__(self, pad, pad_n=None):
         self.rtlink = rtlink.Interface(rtlink.OInterface(1))
-        self.probes = [pad]
+        pad_o = Signal(reset_less=True)
+        self.probes = [pad_o]
         override_en = Signal()
         override_o = Signal()
         self.overrides = [override_en, override_o]
@@ -20,15 +22,19 @@ class Output(Module):
                 pad_k.eq(self.rtlink.o.data)
             ),
             If(override_en,
-                pad.eq(override_o)
+                pad_o.eq(override_o)
             ).Else(
-                pad.eq(pad_k)
+                pad_o.eq(pad_k)
             )
         ]
+        if pad_n is None:
+            self.comb += pad.eq(pad_o)
+        else:
+            self.specials += DifferentialOutput(pad_o, pad, pad_n)
 
 
 class Input(Module):
-    def __init__(self, pad):
+    def __init__(self, pad, pad_n=None):
         self.rtlink = rtlink.Interface(
             rtlink.OInterface(2, 2),
             rtlink.IInterface(1))
@@ -49,8 +55,13 @@ class Input(Module):
         ]
 
         i = Signal()
-        i_d = Signal()
-        self.specials += MultiReg(pad, i, "rio_phy")
+        i_d = Signal(reset_less=True)
+        pad_i = Signal()
+        if pad_n is None:
+            self.comb += pad_i.eq(pad)
+        else:
+            self.specials += DifferentialInput(pad, pad_n, pad_i)
+        self.specials += MultiReg(pad_i, i, "rio_phy")
         self.sync.rio_phy += i_d.eq(i)
         self.comb += [
             self.rtlink.i.stb.eq(