diff --git a/artiq/compiler/testbench/irgen.py b/artiq/compiler/testbench/irgen.py
index 4add27c20..fa1608e12 100644
--- a/artiq/compiler/testbench/irgen.py
+++ b/artiq/compiler/testbench/irgen.py
@@ -1,6 +1,6 @@
 import sys, fileinput
 from pythonparser import diagnostic
-from .. import Module, Source
+from ..module import Module, Source
 
 def main():
     def process_diagnostic(diag):
diff --git a/artiq/compiler/testbench/jit.py b/artiq/compiler/testbench/jit.py
index c1c90dd56..a6d5efcf1 100644
--- a/artiq/compiler/testbench/jit.py
+++ b/artiq/compiler/testbench/jit.py
@@ -1,7 +1,7 @@
 import os, sys, fileinput, ctypes
 from pythonparser import diagnostic
 from llvmlite_artiq import binding as llvm
-from .. import Module, Source
+from ..module import Module, Source
 from ..targets import NativeTarget
 
 def main():
diff --git a/artiq/compiler/testbench/llvmgen.py b/artiq/compiler/testbench/llvmgen.py
index 33500ec8b..21f010a76 100644
--- a/artiq/compiler/testbench/llvmgen.py
+++ b/artiq/compiler/testbench/llvmgen.py
@@ -1,7 +1,7 @@
 import sys, fileinput
 from pythonparser import diagnostic
 from llvmlite_artiq import ir as ll
-from .. import Module, Source
+from ..module import Module, Source
 from ..targets import NativeTarget
 
 def main():
diff --git a/artiq/compiler/testbench/perf.py b/artiq/compiler/testbench/perf.py
index c01e02376..cee4e3c2a 100644
--- a/artiq/compiler/testbench/perf.py
+++ b/artiq/compiler/testbench/perf.py
@@ -1,6 +1,6 @@
 import sys, os
 from pythonparser import diagnostic
-from .. import Module, Source
+from ..module import Module, Source
 from ..targets import OR1KTarget
 from . import benchmark
 
diff --git a/artiq/compiler/testbench/perf_embedding.py b/artiq/compiler/testbench/perf_embedding.py
index 258978eac..cc7a8f31b 100644
--- a/artiq/compiler/testbench/perf_embedding.py
+++ b/artiq/compiler/testbench/perf_embedding.py
@@ -2,7 +2,7 @@ import sys, os
 from pythonparser import diagnostic
 from ...protocols.file_db import FlatFileDB
 from ...master.worker_db import DeviceManager
-from .. import Module
+from ..module import Module
 from ..embedding import Stitcher
 from ..targets import OR1KTarget
 from . import benchmark
diff --git a/artiq/compiler/testbench/shlib.py b/artiq/compiler/testbench/shlib.py
index 97c19f11b..47209a979 100644
--- a/artiq/compiler/testbench/shlib.py
+++ b/artiq/compiler/testbench/shlib.py
@@ -1,6 +1,6 @@
 import sys, os
 from pythonparser import diagnostic
-from .. import Module, Source
+from ..module import Module, Source
 from ..targets import OR1KTarget
 
 def main():
diff --git a/artiq/compiler/testbench/signature.py b/artiq/compiler/testbench/signature.py
index 98d4687fb..d877e2794 100644
--- a/artiq/compiler/testbench/signature.py
+++ b/artiq/compiler/testbench/signature.py
@@ -1,6 +1,7 @@
 import sys, fileinput
 from pythonparser import diagnostic
-from .. import types, iodelay, Module, Source
+from ..module import Module, Source
+from .. import types, iodelay
 
 def main():
     if len(sys.argv) > 1 and sys.argv[1] == "+diag":
diff --git a/artiq/language/types.py b/artiq/language/types.py
index 66a8b1b89..e7e4e64bb 100644
--- a/artiq/language/types.py
+++ b/artiq/language/types.py
@@ -6,7 +6,7 @@ annotations.
 from artiq.compiler import types, builtins
 
 __all__ = ["TNone", "TBool", "TInt32", "TInt64", "TFloat",
-           "TStr", "TList", "TRange32", "TRange64"]
+           "TStr", "TList", "TRange32", "TRange64", "TVar"]
 
 TNone      = builtins.TNone()
 TBool      = builtins.TBool()
@@ -17,3 +17,4 @@ TStr       = builtins.TStr()
 TList      = builtins.TList
 TRange32   = builtins.TRange(builtins.TInt(types.TValue(32)))
 TRange64   = builtins.TRange(builtins.TInt(types.TValue(64)))
+TVar       = types.TVar