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sawg: add register after hbf for timing

This commit is contained in:
Robert Jördens 2017-06-12 23:08:27 +02:00
parent 315338fca9
commit e229edd5d5
1 changed files with 1 additions and 1 deletions
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artiq/gateware/dsp/sawg.py
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@ -172,7 +172,7 @@ class Channel(Module, SatAddMixin):
Cat(a1.clr, a2.clr, b.clr).eq(cfg.clr), Cat(a1.clr, a2.clr, b.clr).eq(cfg.clr),
] ]
for i in range(parallelism): for i in range(parallelism):
self.comb += [ self.sync += [
b.xi[i].eq(self.sat_add(hbf[0].o[i], b.xi[i].eq(self.sat_add(hbf[0].o[i],
limits=cfg.limits[0], limits=cfg.limits[0],
clipped=cfg.clipped[0])), clipped=cfg.clipped[0])),