diff --git a/artiq/gateware/test/dsp/test_sawg_fe.py b/artiq/gateware/test/dsp/test_sawg_fe.py
index c6725656a..caac32a5c 100644
--- a/artiq/gateware/test/dsp/test_sawg_fe.py
+++ b/artiq/gateware/test/dsp/test_sawg_fe.py
@@ -40,6 +40,7 @@ class SAWGTest(unittest.TestCase):
         self.rtio_manager.patch(sawg)
         self.core = sim_devices.Core({})
         self.core.coarse_ref_period = 6.66666
+        self.core.ref_multiplier = 1
         self.t = self.core.coarse_ref_period
         self.channel = mg.ClockDomainsRenamer({"rio_phy": "sys"})(
             Channel(width=16, parallelism=2))