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wrpll: new collector from Weida/Tom

This commit is contained in:
Sebastien Bourdeauducq 2020-01-24 10:31:52 +08:00
parent dee16edb78
commit dfa033eb87
2 changed files with 26 additions and 9 deletions
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5
artiq/gateware/drtio/wrpll/core.py
View File

@ -79,6 +79,9 @@ class WRPLL(Module, AutoCSR):
self.submodules.ddmtd_helper = DDMTD(ddmtd_counter, ddmtd_inputs.rec_clk) self.submodules.ddmtd_helper = DDMTD(ddmtd_counter, ddmtd_inputs.rec_clk)
self.submodules.ddmtd_main = DDMTD(ddmtd_counter, ddmtd_inputs.main_xo) self.submodules.ddmtd_main = DDMTD(ddmtd_counter, ddmtd_inputs.main_xo)
collector_update = Signal()
self.sync.helper += collector_update.eq(ddmtd_counter == (2**N - 1))
filter_cd = ClockDomainsRenamer("filter") filter_cd = ClockDomainsRenamer("filter")
self.submodules.collector = filter_cd(Collector(N)) self.submodules.collector = filter_cd(Collector(N))
self.submodules.filter_helper = filter_cd(thls.make(filters.helper, data_width=48)) self.submodules.filter_helper = filter_cd(thls.make(filters.helper, data_width=48))
@ -98,7 +101,7 @@ class WRPLL(Module, AutoCSR):
] ]
self.comb += [ self.comb += [
self.filter_main.input.eq(self.collector.output), self.filter_main.input.eq(self.collector.output),
self.filter_main.input_stb.eq(self.collector.output_update) self.filter_main.input_stb.eq(collector_update)
] ]
self.sync.helper += [ self.sync.helper += [

30
artiq/gateware/drtio/wrpll/ddmtd.py
View File

@ -131,20 +131,19 @@ class DDMTD(Module, AutoCSR):
class Collector(Module): class Collector(Module):
def __init__(self, N): def __init__(self, N):
self.tag_helper = Signal(N) self.tag_helper = Signal((N, True))
self.tag_helper_update = Signal() self.tag_helper_update = Signal()
self.tag_main = Signal(N) self.tag_main = Signal((N, True))
self.tag_main_update = Signal() self.tag_main_update = Signal()
self.output = Signal((N, True)) self.output = Signal((N + 1, True))
self.output_update = Signal(N)
# # # # # #
fsm = FSM(reset_state="IDLE") fsm = FSM(reset_state="IDLE")
self.submodules += fsm self.submodules += fsm
tag_collector = Signal(N) tag_collector = Signal((N + 1, True))
fsm.act("IDLE", fsm.act("IDLE",
If(self.tag_main_update & self.tag_helper_update, If(self.tag_main_update & self.tag_helper_update,
NextValue(tag_collector, 0), NextValue(tag_collector, 0),
@ -160,17 +159,32 @@ class Collector(Module):
fsm.act("WAITHELPER", fsm.act("WAITHELPER",
If(self.tag_helper_update, If(self.tag_helper_update,
NextValue(tag_collector, tag_collector - self.tag_helper), NextValue(tag_collector, tag_collector - self.tag_helper),
NextState("UPDATE") NextState("LEADCHECK")
) )
) )
fsm.act("WAITMAIN", fsm.act("WAITMAIN",
If(self.tag_main_update, If(self.tag_main_update,
NextValue(tag_collector, tag_collector + self.tag_main), NextValue(tag_collector, tag_collector + self.tag_main),
NextState("UPDATE") NextState("LAGCHECK")
) )
) )
# To compensate DDMTD counter roll-over when main is ahead of roll-over
# and helper is after roll-over
fsm.act("LEADCHECK",
If(tag_collector > 0,
NextValue(tag_collector, tag_collector - (2**N - 1))
),
NextState("UPDATE")
)
# To compensate DDMTD counter roll-over when helper is ahead of roll-over
# and main is after roll-over
fsm.act("LAGCHECK",
If(tag_collector < 0,
NextValue(tag_collector, tag_collector + (2**N - 1))
),
NextState("UPDATE")
)
fsm.act("UPDATE", fsm.act("UPDATE",
NextValue(self.output, tag_collector), NextValue(self.output, tag_collector),
NextState("IDLE") NextState("IDLE")
) )
self.sync += self.output_update.eq(self.tag_helper_update)