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sayma: clock JESD204 from GTP CLK2 

This frees up GTP CLK1, which is routable to the SFP quads, for DRTIO.
This commit is contained in:
Sebastien Bourdeauducq 2018-06-21 22:32:41 +08:00
parent b28ff587c5
commit de7d64d482
3 changed files with 4 additions and 4 deletions
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2
artiq/firmware/libboard_artiq/hmc830_7043.rs
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@ -171,7 +171,7 @@ pub mod hmc7043 {
(true, SYSREF_DIV, 0x08), // 3: DAC1_SYSREF (true, SYSREF_DIV, 0x08), // 3: DAC1_SYSREF
(false, 0, 0x08), // 4: ADC2_CLK (false, 0, 0x08), // 4: ADC2_CLK
(false, 0, 0x08), // 5: ADC2_SYSREF (false, 0, 0x08), // 5: ADC2_SYSREF
(false, 0, 0x08), // 6: GTP_CLK2 (true, FPGA_CLK_DIV, 0x08), // 6: GTP_CLK2
(true, SYSREF_DIV, 0x10), // 7: FPGA_DAC_SYSREF, LVDS (true, SYSREF_DIV, 0x10), // 7: FPGA_DAC_SYSREF, LVDS
(true, FPGA_CLK_DIV, 0x08), // 8: GTP_CLK1 (true, FPGA_CLK_DIV, 0x08), // 8: GTP_CLK1
(false, 0, 0x10), // 9: AMC_MASTER_AUX_CLK (false, 0, 0x10), // 9: AMC_MASTER_AUX_CLK

4
artiq/firmware/runtime/main.rs
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@ -57,9 +57,9 @@ mod moninj;
mod analyzer; mod analyzer;
#[cfg(has_ad9154)] #[cfg(has_ad9154)]
const SYSREF_PHASE_FPGA: u16 = 32; const SYSREF_PHASE_FPGA: u16 = 20;
#[cfg(has_ad9154)] #[cfg(has_ad9154)]
const SYSREF_PHASE_DAC: u16 = 61; const SYSREF_PHASE_DAC: u16 = 31;
fn startup() { fn startup() {
irq::set_mask(0); irq::set_mask(0);

2
artiq/gateware/jesd204_tools.py
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@ -26,7 +26,7 @@ class UltrascaleCRG(Module, AutoCSR):
self.clock_domains.cd_jesd = ClockDomain() self.clock_domains.cd_jesd = ClockDomain()
refclk2 = Signal() refclk2 = Signal()
refclk_pads = platform.request("dac_refclk", 0) refclk_pads = platform.request("dac_refclk", 1)
platform.add_period_constraint(refclk_pads.p, 1e9/self.refclk_freq) platform.add_period_constraint(refclk_pads.p, 1e9/self.refclk_freq)
self.specials += [ self.specials += [
Instance("IBUFDS_GTE3", i_CEB=self.jreset.storage, p_REFCLK_HROW_CK_SEL=0b00, Instance("IBUFDS_GTE3", i_CEB=self.jreset.storage, p_REFCLK_HROW_CK_SEL=0b00,