mirror of https://github.com/m-labs/artiq.git
rtio: fix different address collision detection
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@ -158,8 +158,8 @@ class _OutputManager(Module):
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self.sync.rsys += sequence_error.eq(self.ev.timestamp[fine_ts_width:] <
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buf.timestamp[fine_ts_width:])
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if interface.enable_replace:
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if hasattr(self.ev, "a"):
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different_addresses = self.ev.a != buf.a
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if address_width:
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different_addresses = self.ev.address != buf.address
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else:
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different_addresses = 0
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if fine_ts_width:
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