mirror of https://github.com/m-labs/artiq.git
support .tar flashed idle/startup kernels
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parent
875666f3ec
commit
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@ -13,6 +13,12 @@ dependencies = [
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name = "alloc_list"
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name = "alloc_list"
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version = "0.0.0"
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version = "0.0.0"
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[[package]]
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name = "arrayvec"
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version = "0.7.4"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "96d30a06541fbafbc7f82ed10c06164cfbd2c401138f6addd8404629c4b16711"
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[[package]]
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[[package]]
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name = "bare-metal"
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name = "bare-metal"
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version = "0.2.5"
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version = "0.2.5"
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@ -332,6 +338,7 @@ dependencies = [
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"proto_artiq",
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"proto_artiq",
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"riscv",
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"riscv",
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"smoltcp",
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"smoltcp",
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"tar-no-std",
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"unwind_backtrace",
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"unwind_backtrace",
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]
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]
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@ -416,6 +423,16 @@ dependencies = [
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"syn",
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"syn",
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]
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]
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[[package]]
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name = "tar-no-std"
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version = "0.1.8"
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source = "git+https://git.m-labs.hk/M-Labs/tar-no-std?rev=2ab6dc5#2ab6dc58e5249c59c4eb03eaf3a119bcdd678d32"
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dependencies = [
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"arrayvec",
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"bitflags",
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"log",
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]
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[[package]]
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[[package]]
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name = "unicode-xid"
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name = "unicode-xid"
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version = "0.0.4"
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version = "0.0.4"
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@ -40,3 +40,7 @@ git = "https://git.m-labs.hk/M-Labs/libfringe.git"
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rev = "3ecbe5"
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rev = "3ecbe5"
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default-features = false
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default-features = false
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features = ["alloc"]
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features = ["alloc"]
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[dependencies.tar-no-std]
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git = "https://git.m-labs.hk/M-Labs/tar-no-std"
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rev = "2ab6dc5"
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@ -25,6 +25,8 @@ extern crate board_artiq;
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extern crate logger_artiq;
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extern crate logger_artiq;
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extern crate proto_artiq;
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extern crate proto_artiq;
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extern crate riscv;
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extern crate riscv;
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#[cfg(has_drtio)]
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extern crate tar_no_std;
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use alloc::collections::BTreeMap;
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use alloc::collections::BTreeMap;
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use core::cell::RefCell;
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use core::cell::RefCell;
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@ -2,7 +2,10 @@ use core::{mem, str, cell::{Cell, RefCell}, fmt::Write as FmtWrite};
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use alloc::{vec::Vec, string::{String, ToString}};
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use alloc::{vec::Vec, string::{String, ToString}};
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use byteorder::{ByteOrder, NativeEndian};
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use byteorder::{ByteOrder, NativeEndian};
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use cslice::CSlice;
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use cslice::CSlice;
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#[cfg(has_drtio)]
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use tar_no_std::TarArchiveRef;
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use dyld::elf;
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use io::{Read, Write, Error as IoError};
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use io::{Read, Write, Error as IoError};
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#[cfg(has_drtio)]
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#[cfg(has_drtio)]
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use io::Cursor;
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use io::Cursor;
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@ -45,6 +48,9 @@ pub enum Error<T> {
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#[fail(display = "DDMA error: {}", _0)]
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#[fail(display = "DDMA error: {}", _0)]
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Ddma(#[cause] remote_dma::Error),
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Ddma(#[cause] remote_dma::Error),
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#[cfg(has_drtio)]
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#[cfg(has_drtio)]
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#[fail(display = "subkernel destination is down")]
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DestinationDown,
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#[cfg(has_drtio)]
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#[fail(display = "subkernel error: {}", _0)]
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#[fail(display = "subkernel error: {}", _0)]
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Subkernel(#[cause] SubkernelError),
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Subkernel(#[cause] SubkernelError),
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#[cfg(has_drtio)]
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#[cfg(has_drtio)]
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@ -309,6 +315,63 @@ fn kern_run(session: &mut Session) -> Result<(), Error<SchedError>> {
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kern_acknowledge()
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kern_acknowledge()
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}
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}
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fn process_flash_kernel(io: &Io, _aux_mutex: &Mutex, _subkernel_mutex: &Mutex,
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_routing_table: &drtio_routing::RoutingTable,
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_up_destinations: &Urc<RefCell<[bool; drtio_routing::DEST_COUNT]>>,
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session: &mut Session, kernel: &[u8]
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) -> Result<(), Error<SchedError>> {
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// handle ELF and TAR files
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if kernel[0] == elf::ELFMAG0 && kernel[1] == elf::ELFMAG1 &&
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kernel[2] == elf::ELFMAG2 && kernel[3] == elf::ELFMAG3 {
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// assume ELF file, proceed as before
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unsafe {
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// make a copy as kernel CPU cannot read SPI directly
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kern_load(io, session, Vec::from(kernel).as_ref())
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}
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} else {
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#[cfg(has_drtio)]
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{
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let archive = TarArchiveRef::new(kernel);
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let entries = archive.entries();
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let mut main_lib: Option<&[u8]> = None;
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for entry in entries {
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if entry.filename().as_str() == "main.elf" {
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main_lib = Some(entry.data());
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} else {
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// subkernel filename must be in format:
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// "<subkernel id> <destination>.elf"
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let filename = entry.filename();
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let mut iter = filename.as_str().split_whitespace();
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let sid: u32 = iter.next().unwrap()
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.parse().unwrap();
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let dest: u8 = iter.next().unwrap()
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.strip_suffix(".elf").unwrap()
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.parse().unwrap();
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let up = {
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let up_destinations = _up_destinations.borrow();
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up_destinations[dest as usize]
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};
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if up {
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let subkernel_lib = entry.data().to_vec();
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subkernel::add_subkernel(io, _subkernel_mutex, sid, dest, subkernel_lib)?;
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subkernel::upload(io, _aux_mutex, _subkernel_mutex, _routing_table, sid)?;
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} else {
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return Err(Error::DestinationDown);
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}
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}
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}
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unsafe {
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kern_load(io, session, Vec::from(main_lib.unwrap()).as_ref())
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}
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}
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#[cfg(not(has_drtio))]
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{
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unexpected!("multi-kernel libraries are not supported in standalone systems")
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}
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}
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}
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fn process_host_message(io: &Io, _aux_mutex: &Mutex, _ddma_mutex: &Mutex, _subkernel_mutex: &Mutex,
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fn process_host_message(io: &Io, _aux_mutex: &Mutex, _ddma_mutex: &Mutex, _subkernel_mutex: &Mutex,
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_routing_table: &drtio_routing::RoutingTable, stream: &mut TcpStream,
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_routing_table: &drtio_routing::RoutingTable, stream: &mut TcpStream,
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session: &mut Session) -> Result<(), Error<SchedError>> {
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session: &mut Session) -> Result<(), Error<SchedError>> {
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@ -777,11 +840,17 @@ fn flash_kernel_worker(io: &Io, aux_mutex: &Mutex,
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config::read(config_key, |result| {
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config::read(config_key, |result| {
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match result {
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match result {
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Ok(kernel) => unsafe {
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Ok(kernel) => {
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// kernel CPU cannot access the SPI flash address space directly,
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// process .ELF or .TAR kernels
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// so make a copy.
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let res = process_flash_kernel(io, aux_mutex, subkernel_mutex, routing_table, up_destinations, &mut session, kernel);
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kern_load(io, &mut session, Vec::from(kernel).as_ref())
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#[cfg(has_drtio)]
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},
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match res {
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// wait to establish the DRTIO connection
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Err(Error::DestinationDown) => io.sleep(500)?,
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_ => ()
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}
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res
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}
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_ => Err(Error::KernelNotFound)
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_ => Err(Error::KernelNotFound)
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}
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}
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})?;
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})?;
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@ -249,6 +249,7 @@
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lockFile = ./artiq/firmware/Cargo.lock;
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lockFile = ./artiq/firmware/Cargo.lock;
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outputHashes = {
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outputHashes = {
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"fringe-1.2.1" = "sha256-m4rzttWXRlwx53LWYpaKuU5AZe4GSkbjHS6oINt5d3Y=";
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"fringe-1.2.1" = "sha256-m4rzttWXRlwx53LWYpaKuU5AZe4GSkbjHS6oINt5d3Y=";
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"tar-no-std-0.1.8" = "sha256-xm17108v4smXOqxdLvHl9CxTCJslmeogjm4Y87IXFuM=";
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};
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};
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};
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};
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nativeBuildInputs = [
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nativeBuildInputs = [
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