diff --git a/artiq/gateware/targets/efc.py b/artiq/gateware/targets/efc.py
index 92cd2e771..91ad4a022 100644
--- a/artiq/gateware/targets/efc.py
+++ b/artiq/gateware/targets/efc.py
@@ -109,6 +109,38 @@ class Satellite(BaseSoC, AMPSoC):
                 Subsignal('cs_n', Pins('fmc0:LA31_N fmc0:LA31_P fmc0:HB19_P fmc0:LA30_P')),
                 IOStandard("LVCMOS18")),
             ('dac_rst', 0, Pins('fmc0:HB16_P'), IOStandard("LVCMOS18")),
+            ('dac_din', 0,
+                Subsignal('data', Pins('fmc0:HA06_N fmc0:HA06_P fmc0:HA07_N fmc0:HA02_N fmc0:HA07_P fmc0:HA02_P fmc0:HA03_N fmc0:HA03_P fmc0:HA04_N fmc0:HA04_P fmc0:HA05_N fmc0:HA05_P fmc0:HA00_CC_N fmc0:HA01_CC_N')),
+                Subsignal('clk', Pins('fmc0:HA00_CC_P')),
+                IOStandard('LVCMOS18')),
+            ('dac_din', 1,
+                Subsignal('data', Pins('fmc0:LA09_P fmc0:LA09_N fmc0:LA07_N fmc0:LA08_N fmc0:LA07_P fmc0:LA08_P fmc0:LA05_N fmc0:LA04_N fmc0:LA05_P fmc0:LA06_N fmc0:LA04_P fmc0:LA03_N fmc0:LA03_P fmc0:LA06_P')),
+                Subsignal('clk', Pins('fmc0:LA00_CC_P')),
+                IOStandard('LVCMOS18')),
+            ('dac_din', 2,
+                Subsignal('data', Pins('fmc0:HA14_N fmc0:HA14_P fmc0:HA12_N fmc0:HA12_P fmc0:HA13_N fmc0:HA10_N fmc0:HA10_P fmc0:HA11_N fmc0:HA11_P fmc0:HA13_P fmc0:HA08_N fmc0:HA08_P fmc0:HA09_N fmc0:HA09_P')),
+                Subsignal('clk', Pins('fmc0:HA01_CC_P')),
+                IOStandard('LVCMOS18')),
+            ('dac_din', 3,
+                Subsignal('data', Pins('fmc0:LA14_N fmc0:LA15_N fmc0:LA16_N fmc0:LA15_P fmc0:LA14_P fmc0:LA13_N fmc0:LA16_P fmc0:LA13_P fmc0:LA11_N fmc0:LA12_N fmc0:LA11_P fmc0:LA12_P fmc0:LA10_N fmc0:LA10_P')),
+                Subsignal('clk', Pins('fmc0:LA01_CC_P')),
+                IOStandard('LVCMOS18')),
+            ('dac_din', 4,
+                Subsignal('data', Pins('fmc0:HA22_N fmc0:HA19_N fmc0:HA22_P fmc0:HA21_N fmc0:HA21_P fmc0:HA19_P fmc0:HA18_CC_N fmc0:HA20_N fmc0:HA20_P fmc0:HA18_CC_P fmc0:HA15_N fmc0:HA15_P fmc0:HA16_N fmc0:HA16_P')),
+                Subsignal('clk', Pins('fmc0:HA17_CC_P')),
+                IOStandard('LVCMOS18')),
+            ('dac_din', 5,
+                Subsignal('data', Pins('fmc0:LA24_N fmc0:LA25_N fmc0:LA24_P fmc0:LA25_P fmc0:LA21_N fmc0:LA21_P fmc0:LA22_N fmc0:LA22_P fmc0:LA23_N fmc0:LA23_P fmc0:LA19_N fmc0:LA19_P fmc0:LA20_N fmc0:LA20_P')),
+                Subsignal('clk', Pins('fmc0:LA17_CC_P')),
+                IOStandard('LVCMOS18')),
+            ('dac_din', 6,
+                Subsignal('data', Pins('fmc0:HB08_N fmc0:HB08_P fmc0:HB07_N fmc0:HB07_P fmc0:HB04_N fmc0:HB04_P fmc0:HB01_N fmc0:HB05_N fmc0:HB01_P fmc0:HB05_P fmc0:HB02_N fmc0:HB02_P fmc0:HB03_N fmc0:HB03_P')),
+                Subsignal('clk', Pins('fmc0:HB00_CC_P')),
+                IOStandard('LVCMOS18')),
+            ('dac_din', 7,
+                Subsignal('data', Pins('fmc0:HB13_N fmc0:HB12_N fmc0:HB13_P fmc0:HB12_P fmc0:HB15_N fmc0:HB15_P fmc0:HB11_N fmc0:HB09_N fmc0:HB09_P fmc0:HB14_N fmc0:HB14_P fmc0:HB10_N fmc0:HB10_P fmc0:HB11_P')),
+                Subsignal('clk', Pins('fmc0:HB06_CC_P')),
+                IOStandard('LVCMOS18')),
         ]
 
         platform.add_extension(shuttler_io)