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dsp.fir: pipeline final systolic adder

This commit is contained in:
Robert Jördens 2017-06-29 11:33:19 +02:00
parent 32a33500c8
commit dca662a743
1 changed files with 2 additions and 2 deletions
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4
artiq/gateware/dsp/fir.py
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@ -70,7 +70,7 @@ class ParallelFIR(Module):
# input and output: old to new, decreasing delay # input and output: old to new, decreasing delay
self.i = [Signal((width, True)) for i in range(p)] self.i = [Signal((width, True)) for i in range(p)]
self.o = [Signal((width, True)) for i in range(p)] self.o = [Signal((width, True)) for i in range(p)]
self.latency = (n + 1)//2//p + 1 self.latency = (n + 1)//2//p + 2
w = _widths[arch] w = _widths[arch]
c_max = max(abs(c) for c in coefficients) c_max = max(abs(c) for c in coefficients)
@ -93,7 +93,7 @@ class ParallelFIR(Module):
for delay in range(p): for delay in range(p):
o = Signal((w.P, True), reset_less=True) o = Signal((w.P, True), reset_less=True)
self.comb += self.o[delay].eq(o >> c_shift) self.sync += self.o[delay].eq(o >> c_shift)
# Make products # Make products
tap = delay tap = delay
for i, c in enumerate(cs): for i, c in enumerate(cs):