From dca662a743f15796295260b0bdc4f518209415fd Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Thu, 29 Jun 2017 11:33:19 +0200 Subject: [PATCH] dsp.fir: pipeline final systolic adder --- artiq/gateware/dsp/fir.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/artiq/gateware/dsp/fir.py b/artiq/gateware/dsp/fir.py index 64659f305..4efa46e44 100644 --- a/artiq/gateware/dsp/fir.py +++ b/artiq/gateware/dsp/fir.py @@ -70,7 +70,7 @@ class ParallelFIR(Module): # input and output: old to new, decreasing delay self.i = [Signal((width, True)) for i in range(p)] self.o = [Signal((width, True)) for i in range(p)] - self.latency = (n + 1)//2//p + 1 + self.latency = (n + 1)//2//p + 2 w = _widths[arch] c_max = max(abs(c) for c in coefficients) @@ -93,7 +93,7 @@ class ParallelFIR(Module): for delay in range(p): o = Signal((w.P, True), reset_less=True) - self.comb += self.o[delay].eq(o >> c_shift) + self.sync += self.o[delay].eq(o >> c_shift) # Make products tap = delay for i, c in enumerate(cs):