mirror of
https://github.com/m-labs/artiq.git
synced 2024-12-25 03:08:27 +08:00
spi: have write() delay by transfer duration
This commit is contained in:
parent
423ca03f3b
commit
dc6d116824
@ -198,11 +198,11 @@ class SPIMaster:
|
||||
the previous transfer's read data is available in the
|
||||
``data`` register.
|
||||
|
||||
This method advances the timeline by the duration of the
|
||||
RTIO-to-Wishbone bus transaction (three RTIO clock cycles).
|
||||
This method advances the timeline by the duration of the SPI transfer.
|
||||
If a transfer is to be chained, the timeline needs to be rewound.
|
||||
"""
|
||||
rtio_output(now_mu(), self.channel, SPI_DATA_ADDR, data)
|
||||
delay_mu(3*self.ref_period_mu)
|
||||
delay_mu(self.xfer_period_mu + self.write_period_mu)
|
||||
|
||||
@kernel
|
||||
def read_async(self):
|
||||
|
Loading…
Reference in New Issue
Block a user