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test/full_stack: use Ethernet

This commit is contained in:
Sebastien Bourdeauducq 2015-04-28 01:33:37 +08:00
parent 8a19766278
commit dc14728264
1 changed files with 7 additions and 7 deletions
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14
artiq/test/full_stack.py
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@ -5,7 +5,7 @@ from fractions import Fraction
from artiq import *
from artiq.language.units import DimensionError
from artiq.coredevice import comm_serial, core, runtime_exceptions, rtio
from artiq.coredevice import comm_tcp, core, runtime_exceptions, rtio
from artiq.sim import devices as sim_devices
@ -13,7 +13,7 @@ core_device = os.getenv("ARTIQ_CORE_DEVICE")
def _run_on_device(k_class, **parameters):
comm = comm_serial.Comm(serial_dev=core_device)
comm = comm_tcp.Comm(host=core_device)
try:
coredev = core.Core(comm=comm)
k_inst = k_class(core=coredev, **parameters)
@ -208,7 +208,7 @@ class ExecutionCase(unittest.TestCase):
self.assertEqual(l_device, l_host)
def test_misc(self):
comm = comm_serial.Comm(serial_dev=core_device)
comm = comm_tcp.Comm(host=core_device)
try:
coredev = core.Core(comm=comm)
uut = _Misc(core=coredev)
@ -249,7 +249,7 @@ class ExecutionCase(unittest.TestCase):
self.assertEqual(t_device, t_host)
def test_rpc_exceptions(self):
comm = comm_serial.Comm(serial_dev=core_device)
comm = comm_tcp.Comm(host=core_device)
try:
uut = _RPCExceptions(core=core.Core(comm=comm))
with self.assertRaises(_MyException):
@ -312,7 +312,7 @@ class RTIOCase(unittest.TestCase):
# (C11 and C13 on Papilio Pro)
def test_loopback(self):
npulses = 4
comm = comm_serial.Comm(serial_dev=core_device)
comm = comm_tcp.Comm(host=core_device)
try:
coredev = core.Core(comm=comm)
uut = _RTIOLoopback(
@ -327,7 +327,7 @@ class RTIOCase(unittest.TestCase):
comm.close()
def test_underflow(self):
comm = comm_serial.Comm(serial_dev=core_device)
comm = comm_tcp.Comm(host=core_device)
try:
coredev = core.Core(comm=comm)
uut = _RTIOUnderflow(
@ -340,7 +340,7 @@ class RTIOCase(unittest.TestCase):
comm.close()
def test_sequence_error(self):
comm = comm_serial.Comm(serial_dev=core_device)
comm = comm_tcp.Comm(host=core_device)
try:
coredev = core.Core(comm=comm)
uut = _RTIOSequenceError(