mirror of https://github.com/m-labs/artiq.git
coredevice: adf5356: fix/adjust docs
Signed-off-by: Etienne Wodey <wodey@iqo.uni-hannover.de>
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@ -32,11 +32,6 @@ SPI_CONFIG = (
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ADF5356_MIN_VCO_FREQ = int64(3.4 * GHz)
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ADF5356_MAX_VCO_FREQ = int64(6.8 * GHz)
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ADF5356_MAX_OUTA_FREQ = ADF5356_MAX_VCO_FREQ
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ADF5356_MIN_OUTA_FREQ = ADF5356_MIN_VCO_FREQ / 64
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ADF5356_MAX_OUTB_FREQ = ADF5356_MAX_VCO_FREQ * 2
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ADF5356_MIN_OUTB_FREQ = ADF5356_MIN_VCO_FREQ * 2
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ADF5356_MAX_FREQ_PFD = int32(125.0 * MHz)
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ADF5356_MODULUS1 = int32(1 << 24)
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ADF5356_MAX_MODULUS2 = int32(1 << 28) # FIXME: ADF5356 has 28 bits MOD2
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@ -114,6 +109,11 @@ class ADF5356:
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@kernel
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def read_muxout(self):
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"""
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Read the state of the MUXOUT line.
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By default, this is configured to be the digital lock detection.
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"""
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return bool(self.cpld.read_reg(0) & (1 << (self.channel + 8)))
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@kernel
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@ -346,6 +346,9 @@ class ADF5356:
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return 1 << ADF5356_REG6_RF_DIVIDER_SELECT_GET(self.regs[6])
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def info(self):
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"""
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Return a summary of high-level parameters as a dict.
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"""
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prescaler = ADF5356_REG0_PRESCALER_GET(self.regs[0])
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return {
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# output
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@ -533,11 +536,14 @@ def calculate_pll(f_vco: TInt64, f_pfd: TInt64):
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"""
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Calculate fractional-N PLL parameters such that
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f_vco = f_pfd * (n + (frac1 + frac2/mod2) / mod1)
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``f_vco`` = ``f_pfd`` * (``n`` + (``frac1`` + ``frac2``/``mod2``) / ``mod1``)
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where
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mod1 = 2**24
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mod2 = 2**28
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``mod1 = 2**24`` and ``mod2 <= 2**28``
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:param f_vco: target VCO frequency
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:param f_pfd: PFD frequency
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:return: ``(n, frac1, (frac2_msb, frac2_lsb), (mod2_msb, mod2_lsb))``
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"""
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f_pfd = int64(f_pfd)
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f_vco = int64(f_vco)
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@ -105,10 +105,10 @@ RF generation drivers
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.. automodule:: artiq.coredevice.mirny
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:members:
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:mod:`artiq.coredevice.adf5355` module
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:mod:`artiq.coredevice.adf5356` module
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+++++++++++++++++++++++++++++++++++++++
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.. automodule:: artiq.coredevice.adf5355
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.. automodule:: artiq.coredevice.adf5356
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:members:
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:mod:`artiq.coredevice.spline` module
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