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gateware/serwb/core: cleanup and increase fifo depth

This commit is contained in:
Florent Kermarrec 2017-11-10 10:33:39 +01:00
parent 5dc131636d
commit db82b11f29
1 changed files with 7 additions and 5 deletions
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10
artiq/gateware/serwb/core.py
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@ -12,10 +12,10 @@ class SERWBCore(Module):
depacketizer = Depacketizer(clk_freq)
packetizer = Packetizer()
self.submodules += depacketizer, packetizer
tx_cdc = stream.AsyncFIFO([("data", 32)], 8)
tx_cdc = stream.AsyncFIFO([("data", 32)], 32)
tx_cdc = ClockDomainsRenamer({"write": "sys", "read": "serwb_serdes"})(tx_cdc)
self.submodules += tx_cdc
rx_cdc = stream.AsyncFIFO([("data", 32)], 8)
rx_cdc = stream.AsyncFIFO([("data", 32)], 32)
rx_cdc = ClockDomainsRenamer({"write": "serwb_serdes", "read": "sys"})(rx_cdc)
self.submodules += rx_cdc
self.comb += [
@ -25,10 +25,12 @@ class SERWBCore(Module):
# core --> serdes
packetizer.source.connect(tx_cdc.sink),
If(tx_cdc.source.stb & phy.init.ready,
If(phy.init.ready,
If(tx_cdc.source.stb,
phy.serdes.tx_data.eq(tx_cdc.source.data)
),
tx_cdc.source.ack.eq(phy.init.ready),
tx_cdc.source.ack.eq(1)
),
# serdes --> core
rx_cdc.sink.stb.eq(phy.init.ready),