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serwb: style, use migen, fix imports

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This commit is contained in:
Sebastien Bourdeauducq 2017-08-21 12:35:59 -04:00
parent da90a0fa12
commit dac3a78b75
4 changed files with 13 additions and 15 deletions
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2
artiq/gateware/serwb/etherbone.py
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@ -15,7 +15,7 @@ from migen import *
from misoc.interconnect import stream from misoc.interconnect import stream
from misoc.interconnect import wishbone from misoc.interconnect import wishbone
from amc_rtm_link.packet import * from artiq.gateware.serwb.packet import *
class Packetizer(Module): class Packetizer(Module):

2
artiq/gateware/serwb/kusphy.py
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@ -5,7 +5,7 @@ from migen.genlib.misc import BitSlip
from misoc.cores.code_8b10b import Encoder, Decoder from misoc.cores.code_8b10b import Encoder, Decoder
from amc_rtm_link.phy import PhaseDetector from artiq.gateware.serwb.phy import PhaseDetector
class KUSSerdesPLL(Module): class KUSSerdesPLL(Module):

2
artiq/gateware/serwb/s7phy.py
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@ -5,7 +5,7 @@ from migen.genlib.misc import BitSlip
from misoc.cores.code_8b10b import Encoder, Decoder from misoc.cores.code_8b10b import Encoder, Decoder
from amc_rtm_link.phy import PhaseDetector from artiq.gateware.serwb.phy import PhaseDetector
class S7SerdesPLL(Module): class S7SerdesPLL(Module):

22
artiq/gateware/test/serwb/test_etherbone.py
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@ -1,15 +1,10 @@
#!/usr/bin/env python3 from migen import *
from litex.gen import * from misoc.interconnect.wishbone import SRAM
from misoc.interconnect.stream import Converter
import sys from artiq.gateware.serwb import packet
sys.path.append("../../gateware/") from artiq.gateware.serwb import etherbone
from amc_rtm_link import packet
from amc_rtm_link import etherbone
from litex.soc.interconnect.wishbone import SRAM
from litex.soc.interconnect.stream import Converter
class DUT(Module): class DUT(Module):
@ -57,6 +52,7 @@ class DUT(Module):
# expose wishbone slave # expose wishbone slave
self.wishbone = slave_etherbone.wishbone.bus self.wishbone = slave_etherbone.wishbone.bus
def main_generator(dut): def main_generator(dut):
for i in range(8): for i in range(8):
yield from dut.wishbone.write(0x100 + i, i) yield from dut.wishbone.write(0x100 + i, i)
@ -64,5 +60,7 @@ def main_generator(dut):
data = (yield from dut.wishbone.read(0x100 + i)) data = (yield from dut.wishbone.read(0x100 + i))
print("0x{:08x}".format(data)) print("0x{:08x}".format(data))
dut = DUT()
run_simulation(dut, main_generator(dut), vcd_name="sim.vcd") if __name__ == "__main__":
dut = DUT()
run_simulation(dut, main_generator(dut), vcd_name="sim.vcd")