mirror of https://github.com/m-labs/artiq.git
gateware.spi: rework wb bus sequence
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12252abc8f
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@ -292,14 +292,12 @@ class SPIMaster(Module):
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data_width, clock_width=len(config.div_read),
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bits_width=len(xfer.read_length))
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wb_we = Signal()
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pending = Signal()
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cs = Signal.like(xfer.cs)
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data_read = Signal.like(spi.reg.data)
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data_write = Signal.like(spi.reg.data)
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self.comb += [
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wb_we.eq(bus.cyc & bus.stb & bus.we & (~pending | spi.done)),
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bus.dat_r.eq(
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Array([data_read, xfer.raw_bits(), config.raw_bits()
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])[bus.adr]),
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@ -310,13 +308,6 @@ class SPIMaster(Module):
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spi.div_read.eq(config.div_read),
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]
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self.sync += [
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bus.ack.eq(bus.cyc & bus.stb & (~bus.we | ~pending | spi.done)),
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If(wb_we,
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Array([data_write, xfer.raw_bits(), config.raw_bits()
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])[bus.adr].eq(bus.dat_w)
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),
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config.active.eq(spi.cs),
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config.pending.eq(pending),
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If(spi.done,
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data_read.eq(spi.reg.data),
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),
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@ -327,9 +318,19 @@ class SPIMaster(Module):
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spi.reg.data.eq(data_write),
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pending.eq(0),
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),
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If(wb_we & (bus.adr == 0), # data register
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pending.eq(1),
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bus.ack.eq(bus.cyc & bus.stb & (~bus.we | ~pending | spi.done)),
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If(bus.ack,
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bus.ack.eq(0),
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),
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If(bus.we & bus.ack,
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Array([data_write, xfer.raw_bits(), config.raw_bits()
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])[bus.adr].eq(bus.dat_w),
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If(bus.adr == 0, # data register
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pending.eq(1),
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),
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),
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config.active.eq(spi.cs),
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config.pending.eq(pending),
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]
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# I/O
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