pdq: read/write_reg -> get/set_reg

see also m-labs/pdq#14

artiq/coredevice/pdq.py

@@ -57,7 +57,7 @@ class PDQ(PDQBase):
         self.bus.set_xfer(self.chip_select, 16, 0)
 
     @kernel
-    def write_reg(self, adr, data, board):
+    def set_reg(self, adr, data, board):
         """Set a PDQ register.
 
         :param adr: Address of the register (``_PDQ_ADR_CONFIG``,
@@ -69,7 +69,7 @@ class PDQ(PDQBase):
         delay_mu(self.bus.ref_period_mu)  # get to 20ns min cs high
 
     @kernel
-    def read_reg(self, adr, board):
+    def get_reg(self, adr, board):
         """Get a PDQ register.
 
         :param adr: Address of the register (``_PDQ_ADR_CONFIG``,

artiq/devices/pdq/driver.py

@@ -71,8 +71,8 @@ class PDQ(PDQBase):
             assert written == len(msg), (written, len(msg))
         self.crc = crc8(data, self.crc)
 
-    def write_reg(self, adr, data, board):
-        """Write to a configuration register.
+    def set_reg(self, adr, data, board):
+        """Set a register.
 
         Args:
             board (int): Board to write to (0-0xe), 0xf for all boards.

artiq/devices/pdq/mediator.py

@@ -136,7 +136,7 @@ class _Frame:
             self.pdq.current_frame = self.frame_number
             self.pdq.next_segment = 0
             at_mu(trigger_start_t - self.core.seconds_to_mu(frame_setup))
-            self.pdq.write_frame(self.frame_number)
+            self.pdq.set_frame(self.frame_number)
 
         at_mu(trigger_start_t)
         self.pdq.trigger.pulse(trigger_duration)
@@ -172,7 +172,7 @@ class CompoundPDQ:
             frame._invalidate()
         self.frames.clear()
         for dev in self.pdqs:
-            dev.write_config(reset=0, clk2x=self.clk2x, enable=0, trigger=0,
+            dev.set_config(reset=0, clk2x=self.clk2x, enable=0, trigger=0,
                     aux_miso=self.aux_miso, aux_dac=self.aux_dac, board=0xf)
         self.armed = False
 
@@ -205,7 +205,7 @@ class CompoundPDQ:
             pdq.program(program)
             n += dn
         for pdq in self.pdqs:
-            dev.write_config(reset=0, clk2x=self.clk2x, enable=1, trigger=0,
+            dev.set_config(reset=0, clk2x=self.clk2x, enable=1, trigger=0,
                     aux_miso=self.aux_miso, aux_dac=self.aux_dac, board=0xf)
         self.armed = True
 
@@ -217,6 +217,6 @@ class CompoundPDQ:
         return r
 
     @kernel
-    def write_frame(self, frame):
+    def set_frame(self, frame):
         for pdq in self.pdqs:
-            pdq.write_frame(self.frame_number)
+            pdq.set_frame(self.frame_number)

artiq/devices/pdq/protocol.py

@@ -294,11 +294,11 @@ class PDQBase:
         self.freq = float(freq)
 
     @portable
-    def write_reg(self, adr, data, board):
+    def set_reg(self, adr, data, board):
         raise NotImplementedError
 
     @portable
-    def read_reg(self, adr, board):
+    def get_reg(self, adr, board):
         raise NotImplementedError
 
     @portable
@@ -310,7 +310,7 @@ class PDQBase:
         raise NotImplementedError
 
     @portable
-    def write_config(self, reset=0, clk2x=0, enable=1,
+    def set_config(self, reset=0, clk2x=0, enable=1,
                      trigger=0, aux_miso=0, aux_dac=0b111, board=0xf):
         """Set the configuration register.
 
@@ -332,51 +332,51 @@ class PDQBase:
         """
         config = ((reset << 0) | (clk2x << 1) | (enable << 2) |
                   (trigger << 3) | (aux_miso << 4) | (aux_dac << 5))
-        self.write_reg(PDQ_ADR_CONFIG, config, board)
+        self.set_reg(PDQ_ADR_CONFIG, config, board)
 
     @portable
-    def read_config(self, board=0xf):
+    def get_config(self, board=0xf):
         """Read configuration register.
 
-        .. seealso: :meth:`write_config`
+        .. seealso: :meth:`set_config`
         """
-        return self.read_reg(PDQ_ADR_CONFIG, board)
+        return self.get_reg(PDQ_ADR_CONFIG, board)
 
     @portable
-    def write_crc(self, crc=0, board=0xf):
+    def set_crc(self, crc=0, board=0xf):
         """Set/reset the checksum register.
 
         Args:
             crc (int): Checksum value to write.
             board (int): Board to write to (0-0xe), 0xf for all boards.
         """
-        self.write_reg(PDQ_ADR_CRC, crc, board)
+        self.set_reg(PDQ_ADR_CRC, crc, board)
 
     @portable
-    def read_crc(self, board=0xf):
+    def get_crc(self, board=0xf):
         """Read checksum register.
 
-        .. seealso:: :meth:`write_crc`
+        .. seealso:: :meth:`set_crc`
         """
-        return self.read_reg(PDQ_ADR_CRC, board)
+        return self.get_reg(PDQ_ADR_CRC, board)
 
     @portable
-    def write_frame(self, frame, board=0xf):
+    def set_frame(self, frame, board=0xf):
         """Set the current frame.
 
         Args:
             frame (int): Frame to select.
             board (int): Board to write to (0-0xe), 0xf for all boards.
         """
-        self.write_reg(PDQ_ADR_FRAME, frame, board)
+        self.set_reg(PDQ_ADR_FRAME, frame, board)
 
     @portable
-    def read_frame(self, board=0xf):
+    def get_frame(self, board=0xf):
         """Read frame selection register.
 
-        .. seealso:: :meth:`write_frame`
+        .. seealso:: :meth:`set_frame`
         """
-        return self.read_reg(PDQ_ADR_FRAME, board)
+        return self.get_reg(PDQ_ADR_FRAME, board)
 
     def program_segments(self, segments, data):
         """Append the wavesynth lines to the given segments.

artiq/frontend/aqctl_pdq.py

@@ -43,10 +43,10 @@ def main():
     try:
         if args.reset:
             dev.write(b"")  # flush eop
-            dev.write_config(reset=True)
+            dev.set_config(reset=True)
             time.sleep(.1)
 
-        dev.write_crc(0)
+        dev.set_crc(0)
         dev.checksum = 0
 
         simple_server_loop({"pdq": dev}, bind_address_from_args(args),

artiq/test/test_pdq.py

@@ -17,7 +17,7 @@ class TestPdq(unittest.TestCase):
         self.synth = Synthesizer(3, _test_program)
 
     def test_reset(self):
-        self.dev.write_config(reset=True)
+        self.dev.set_config(reset=True)
         buf = self.dev.dev.getvalue()
         self.assertEqual(buf, b"\xa5\x02\xf8\xe5\xa5\x03")
 
@@ -26,9 +26,9 @@ class TestPdq(unittest.TestCase):
         self.dev.program(_test_program)
 
     def test_cmd_program(self):
-        self.dev.write_config(enable=False)
+        self.dev.set_config(enable=False)
         self.dev.program(_test_program)
-        self.dev.write_config(enable=True, trigger=True)
+        self.dev.set_config(enable=True, trigger=True)
         return self.dev.dev.getvalue()
 
     def test_synth(self):