ad9910: add read64()

Signed-off-by: Robert Jördens <rj@quartiq.de>
This commit is contained in:
Robert Jördens 2018-12-07 21:27:00 +00:00
parent baf88050fd
commit d90eb3ae88
2 changed files with 42 additions and 1 deletions

View File

@ -181,6 +181,28 @@ class AD9910:
self.bus.write(0)
return self.bus.read()
@kernel
def read64(self, addr):
"""Read from 64 bit register.
:param addr: Register address
:return: 64 bit integer register value
"""
self.bus.set_config_mu(urukul.SPI_CONFIG, 8,
urukul.SPIT_DDS_WR, self.chip_select)
self.bus.write((addr | 0x80) << 24)
self.bus.set_config_mu(
urukul.SPI_CONFIG | spi.SPI_INPUT, 32,
urukul.SPIT_DDS_RD, self.chip_select)
self.bus.write(0)
self.bus.set_config_mu(
urukul.SPI_CONFIG | spi.SPI_END | spi.SPI_INPUT, 32,
urukul.SPIT_DDS_RD, self.chip_select)
self.bus.write(0)
hi = self.bus.read()
lo = self.bus.read()
return (int64(hi) << 32) | lo
@kernel
def write64(self, addr, data_high, data_low):
"""Write to 64 bit register.

View File

@ -1,6 +1,6 @@
from artiq.experiment import *
from artiq.test.hardware_testbench import ExperimentCase
from artiq.coredevice.ad9910 import _AD9910_REG_FTW
from artiq.coredevice.ad9910 import _AD9910_REG_FTW, _AD9910_REG_PROFILE0
from artiq.coredevice.urukul import (
urukul_sta_smp_err, CFG_CLK_SEL0, CFG_CLK_SEL1)
@ -46,6 +46,19 @@ class AD9910Exp(EnvExperiment):
self.set_dataset("ftw_set", self.dev.frequency_to_ftw(f))
self.set_dataset("ftw_get", self.dev.read32(_AD9910_REG_FTW))
@kernel
def read_write64(self):
self.core.break_realtime()
self.dev.cpld.init()
self.dev.init()
lo = 0x12345678
hi = 0x09abcdef
self.dev.write64(_AD9910_REG_PROFILE0, hi, lo)
self.dev.cpld.io_update.pulse_mu(8)
read = self.dev.read64(_AD9910_REG_PROFILE0)
self.set_dataset("write", (int64(hi) << 32) | lo)
self.set_dataset("read", read)
@kernel
def set_speed(self):
self.core.break_realtime()
@ -170,6 +183,12 @@ class AD9910Test(ExperimentCase):
ftw_set = self.dataset_mgr.get("ftw_set")
self.assertEqual(ftw_get, ftw_set)
def test_read_write64(self):
self.execute(AD9910Exp, "read_write64")
write = self.dataset_mgr.get("write")
read = self.dataset_mgr.get("read")
self.assertEqual(hex(write), hex(read))
def test_set_speed(self):
self.execute(AD9910Exp, "set_speed")
dt = self.dataset_mgr.get("dt")