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rtio: add SERDES TTL (WIP)
This commit is contained in:
Yann Sionneau
parent
cf16da5763
commit
d90dff4ef1
58
artiq/gateware/rtio/phy/ttl_serdes_7series.py
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58
artiq/gateware/rtio/phy/ttl_serdes_7series.py
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@ -0,0 +1,58 @@
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from migen.fhdl.std import *
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from artiq.gateware.rtio.phy import ttl_serdes_generic
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class OSerdese2(Module):
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def __init__(self, pad):
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self.o = o = Signal(8)
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self.oe = oe = Signal()
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self.t = t = Signal()
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self.specials += Instance("OSERDESE2", p_DATA_RATE_OQ="DDR",
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p_DATA_RATE_TQ="DDR", p_DATA_WIDTH=8,
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p_TRISTATE_WIDTH=1, o_OQ=pad, o_TQ=t,
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i_CLK=ClockSignal("rtiox4"),
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i_CLKDIV=ClockSignal("rio_phy"),
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i_D1=o[0], i_D2=o[1], i_D3=o[2], i_D4=o[3],
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i_D5=o[4], i_D6=o[5], i_D7=o[6], i_D8=o[7],
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i_TCE=1, i_OCE=1, i_RST=ResetSignal(),
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i_T1=~oe)
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class IOSerdese2(Module):
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def __init__(self, pad):
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ts = TSTriple()
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self.o = o = Signal(8)
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self.oe = oe = Signal()
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self.i = i = Signal(8)
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self.specials += ts.get_tristate(pad)
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self.specials += Instance("ISERDESE2", p_DATA_RATE="DDR",
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p_DATA_WIDTH=8,
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p_INTERFACE_TYPE="NETWORKING", p_NUM_CE=1,
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o_Q1=i[7], o_Q2=i[6], o_Q3=i[5], o_Q4=i[4],
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o_Q5=i[3], o_Q6=i[2], o_Q7=i[1], o_Q8=i[0],
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i_D=ts.i, i_CLK=ClockSignal("rtiox4"),
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i_CE1=1, i_RST=ResetSignal(),
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i_CLKDIV=ClockSignal("rio_phy"))
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oserdes = OSerdese2(ts.o)
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self.submodules += oserdes
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self.comb += [
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ts.oe.eq(~oserdes.t),
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oserdes.o.eq(o),
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oserdes.oe.eq(oe)
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]
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class Output(Module):
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def __init__(self, pad):
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serdes = OSerdese2(pad)
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self.submodules += ttl_serdes_generic.Output(serdes, fine_ts_width=3)
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class Inout(Module):
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def __init__(self, pad):
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serdes = IOSerdese2(pad)
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self.submodules += ttl_serdes_generic.InOut(serdes, fine_ts_width=3)
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304
artiq/gateware/rtio/phy/ttl_serdes_generic.py
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304
artiq/gateware/rtio/phy/ttl_serdes_generic.py
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@ -0,0 +1,304 @@
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from migen.fhdl.std import *
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from artiq.gateware.rtio import rtlink
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from migen.genlib.coding import PriorityEncoder
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class Output(Module):
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def __init__(self, serdes, fine_ts_width=0):
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self.rtlink = rtlink.Interface(rtlink.OInterface(1, fine_ts_width=
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fine_ts_width))
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serdes_width = 2**fine_ts_width
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o = Signal()
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previous_o = Signal()
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override_en = Signal()
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override_o = Signal()
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io_o = Signal()
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self.overrides = [override_en, override_o]
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io = serdes
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self.submodules += io
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if fine_ts_width > 0:
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timestamp = Signal(fine_ts_width)
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# dout
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edges = Array([0xff ^ ((1 << i) - 1) for i in range(serdes_width)])
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edge_out = Signal(serdes_width)
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edge_out_n = Signal(serdes_width)
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rise_out = Signal()
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fall_out = Signal()
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self.comb += [
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timestamp.eq(self.rtlink.o.fine_ts),
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edge_out.eq(edges[timestamp]),
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edge_out_n.eq(~edge_out),
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rise_out.eq(~previous_o & o),
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fall_out.eq(previous_o & ~o),
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If(override_en,
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io.o.eq(override_o)
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).Else(
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If(rise_out,
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io.o.eq(edge_out),
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).Elif(fall_out,
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io.o.eq(edge_out_n),
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).Else(
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io.o.eq(Replicate(o, serdes_width)),
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)
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)
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]
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else:
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self.comb += [
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If(override_en,
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io_o.eq(override_o)
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).Else(
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io_o.eq(o)
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)
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]
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self.comb += [
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io.o.eq(io_o),
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]
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self.sync.rio_phy += [
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If(self.rtlink.o.stb,
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o.eq(self.rtlink.o.data),
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),
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previous_o.eq(o),
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]
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class Inout(Module):
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def __init__(self, serdes, fine_ts_width=0):
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self.rtlink = rtlink.Interface(
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rtlink.OInterface(2, 2, fine_ts_width=fine_ts_width),
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rtlink.IInterface(1, fine_ts_width=fine_ts_width))
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self.probes = []
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serdes_width = 2**fine_ts_width
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self.io = io = serdes
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self.submodules += io
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io_o = Signal(serdes_width)
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io_i = Signal(serdes_width)
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o = Signal()
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rising = Signal()
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falling = Signal()
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i0 = Signal()
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self.oe = oe = Signal()
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override_en = Signal()
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override_o = Signal()
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override_oe = Signal()
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self.sensitivity = Signal(2)
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self.overrides = [override_en, override_o, override_oe]
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previous_o = Signal()
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if fine_ts_width > 0:
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# Input
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self.submodules.pe = pe = PriorityEncoder(serdes_width)
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self.sync.rio_phy += i0.eq(io_i[-1])
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self.comb += [
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io_i.eq(io.i),
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rising.eq(~i0 & io_i[-1]),
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falling.eq(i0 & ~io_i[-1]),
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pe.i.eq(io_i ^ Replicate(falling, serdes_width)),
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self.rtlink.i.data.eq(io_i[-1]),
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self.rtlink.i.fine_ts.eq(pe.o),
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]
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# Output
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timestamp = Signal(fine_ts_width)
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edges = Array([0xff ^ ((1 << i) - 1) for i in range(serdes_width)])
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edge_out = Signal(serdes_width)
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edge_out_n = Signal(serdes_width)
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rise_out = Signal()
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fall_out = Signal()
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self.comb += [
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timestamp.eq(self.rtlink.o.fine_ts),
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edge_out.eq(edges[timestamp]),
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edge_out_n.eq(~edge_out),
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rise_out.eq(~previous_o & o),
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fall_out.eq(previous_o & ~o),
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If(override_en,
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io_o.eq(override_o),
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).Else(
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If(rise_out,
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io_o.eq(edge_out),
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).Elif(fall_out,
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io_o.eq(edge_out_n),
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).Else(
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io_o.eq(Replicate(o, serdes_width)),
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)
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)
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]
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else:
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self.comb += [
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io_i.eq(io.i),
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rising.eq(~i0 & io_i),
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falling.eq(i0 & ~io_i),
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If(override_en,
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io_o.eq(override_o)
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).Else(
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io_o.eq(o),
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),
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self.rtlink.i.data.eq(io_i),
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]
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self.comb += [
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io.oe.eq(oe),
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io.o.eq(io_o),
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self.rtlink.i.stb.eq(
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(self.sensitivity[0] & rising) |
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(self.sensitivity[1] & falling)
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),
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]
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self.sync.rio_phy += [
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If(self.rtlink.o.stb,
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If(self.rtlink.o.address == 0, o.eq(self.rtlink.o.data[0])),
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If(self.rtlink.o.address == 1, oe.eq(self.rtlink.o.data[0])),
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),
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If(override_en,
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oe.eq(override_oe)
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),
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previous_o.eq(o),
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]
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self.sync.rio += [
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If(self.rtlink.o.stb & (self.rtlink.o.address == 2),
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self.sensitivity.eq(self.rtlink.o.data)
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)
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]
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class FakeSerdes(Module):
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def __init__(self):
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self.o = o = Signal(8)
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self.oe = oe = Signal(8)
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class FakeIOSerdes(Module):
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def __init__(self):
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self.o = o = Signal(8)
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self.oe = oe = Signal(8)
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self.i = i = Signal(8)
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class OutputTB(Module):
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def __init__(self):
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serdes = FakeSerdes()
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self.o = RenameClockDomains(Output(serdes, fine_ts_width=3),
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{"rio_phy": "sys"})
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self.submodules += self.o
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def gen_simulation(self, selfp):
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yield
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selfp.o.rtlink.o.data = 1
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selfp.o.rtlink.o.fine_ts = 1
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selfp.o.rtlink.o.stb = 1
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yield
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selfp.o.rtlink.o.stb = 0
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yield
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selfp.o.rtlink.o.data = 0
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selfp.o.rtlink.o.fine_ts = 2
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selfp.o.rtlink.o.stb = 1
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yield
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selfp.o.rtlink.o.data = 1
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selfp.o.rtlink.o.fine_ts = 7
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yield
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while True:
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yield
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class InoutTB(Module):
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def __init__(self):
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ioserdes = FakeIOSerdes()
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self.io = RenameClockDomains(Inout(ioserdes, fine_ts_width=3),
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{"rio_phy": "sys"})
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self.submodules += self.io
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def check_input(self, selfp, stb, fine_ts=None):
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if stb != selfp.io.rtlink.i.stb:
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print("KO rtlink.i.stb should be {} but is {}"
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.format(stb, selfp.io.rtlink.i.stb))
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elif fine_ts is not None and fine_ts != selfp.io.rtlink.i.fine_ts:
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print("KO rtlink.i.fine_ts should be {} but is {}"
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.format(fine_ts, selfp.io.rtlink.i.fine_ts))
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else:
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print("OK")
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def check_output(self, selfp, data):
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if selfp.io.io.o != data:
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print("KO io.o should be {} but is {}".format(data, selfp.io.io.o))
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else:
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print("OK")
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def check_output_enable(self, selfp, oe):
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if selfp.io.io.oe != oe:
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print("KO io.oe should be {} but is {}".format(oe, selfp.io.io.oe))
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else:
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print("OK")
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def gen_simulation(self, selfp):
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selfp.io.sensitivity = 0b11 # rising + falling
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self.check_output_enable(selfp, 0)
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yield
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selfp.io.io.i = 0b11111110 # rising edge at fine_ts = 1
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yield
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self.check_input(selfp, stb=1, fine_ts=1)
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selfp.io.io.i = 0b01111111 # falling edge at fine_ts = 7
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yield
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self.check_input(selfp, stb=1, fine_ts=7)
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selfp.io.io.i = 0b11000000 # rising edge at fine_ts = 6
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yield
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self.check_input(selfp, stb=1, fine_ts=6)
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selfp.io.sensitivity = 0b01 # rising
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selfp.io.io.i = 0b00001111 # falling edge at fine_ts = 4
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yield
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self.check_input(selfp, stb=0) # no strobe, sensitivity is rising edge
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selfp.io.io.i = 0b11110000 # rising edge at fine_ts = 4
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yield
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self.check_input(selfp, stb=1, fine_ts=4)
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selfp.io.rtlink.o.address = 1
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selfp.io.rtlink.o.data = 1
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selfp.io.rtlink.o.stb = 1 # set Output Enable to 1
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yield
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selfp.io.rtlink.o.address = 0
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selfp.io.rtlink.o.data = 1
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selfp.io.rtlink.o.fine_ts = 3 # rising edge at fine_ts = 3
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yield
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self.check_output_enable(selfp, 1)
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yield
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selfp.io.rtlink.o.data = 0
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selfp.io.rtlink.o.fine_ts = 0 # falling edge at fine_ts = 0
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self.check_output(selfp, data=0b11111000)
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yield
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self.check_output(selfp, data=0xFF) # stays at 1
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yield
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selfp.io.rtlink.o.data = 1
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selfp.io.rtlink.o.fine_ts = 7
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self.check_output(selfp, data=0)
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yield
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self.check_output(selfp, data=0)
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yield
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self.check_output(selfp, data=0b10000000)
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while True:
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yield
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if __name__ == "__main__":
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import sys
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from migen.sim.generic import Simulator, TopLevel
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from migen.sim import icarus
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if len(sys.argv) <= 1:
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print("You should run this script with either InoutTB() or OutputTB() "
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"arg")
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sys.exit(1)
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with Simulator(eval(sys.argv[1]), TopLevel("top.vcd", clk_period=int(1/0.125)),
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icarus.Runner(keep_files=False,)) as s:
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s.run(200)
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