mirror of
https://github.com/m-labs/artiq.git
synced 2024-12-22 09:54:00 +08:00
drtio: initialize AD9516 clock chip
This commit is contained in:
parent
54295b1699
commit
d8e9949266
artiq
@ -14,6 +14,9 @@ fn startup() {
|
|||||||
info!("software version {}", include_str!(concat!(env!("OUT_DIR"), "/git-describe")));
|
info!("software version {}", include_str!(concat!(env!("OUT_DIR"), "/git-describe")));
|
||||||
info!("gateware version {}", board::ident(&mut [0; 64]));
|
info!("gateware version {}", board::ident(&mut [0; 64]));
|
||||||
|
|
||||||
|
#[cfg(has_ad9516)]
|
||||||
|
board::ad9516::init().expect("cannot initialize ad9516");
|
||||||
|
|
||||||
loop {}
|
loop {}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -5,6 +5,7 @@ import argparse
|
|||||||
from migen import *
|
from migen import *
|
||||||
from migen.build.generic_platform import *
|
from migen.build.generic_platform import *
|
||||||
|
|
||||||
|
from misoc.cores import spi as spi_csr
|
||||||
from misoc.targets.kc705 import MiniSoC, soc_kc705_args, soc_kc705_argdict
|
from misoc.targets.kc705 import MiniSoC, soc_kc705_args, soc_kc705_argdict
|
||||||
from misoc.integration.soc_core import mem_decoder
|
from misoc.integration.soc_core import mem_decoder
|
||||||
from misoc.integration.builder import builder_args, builder_argdict
|
from misoc.integration.builder import builder_args, builder_argdict
|
||||||
@ -59,6 +60,14 @@ class Master(MiniSoC, AMPSoC):
|
|||||||
tx_pads=tx_pads,
|
tx_pads=tx_pads,
|
||||||
rx_pads=rx_pads,
|
rx_pads=rx_pads,
|
||||||
sys_clk_freq=self.clk_freq)
|
sys_clk_freq=self.clk_freq)
|
||||||
|
|
||||||
|
ad9154_spi = platform.request("ad9154_spi")
|
||||||
|
self.comb += ad9154_spi.en.eq(1)
|
||||||
|
self.submodules.converter_spi = spi_csr.SPIMaster(ad9154_spi)
|
||||||
|
self.csr_devices.append("converter_spi")
|
||||||
|
self.config["CONVERTER_SPI_DAC_CS"] = 0
|
||||||
|
self.config["CONVERTER_SPI_CLK_CS"] = 1
|
||||||
|
self.config["HAS_AD9516"] = None
|
||||||
else:
|
else:
|
||||||
raise ValueError
|
raise ValueError
|
||||||
self.submodules.drtio = DRTIOMaster(self.transceiver)
|
self.submodules.drtio = DRTIOMaster(self.transceiver)
|
||||||
|
@ -175,6 +175,14 @@ class Satellite(BaseSoC):
|
|||||||
tx_pads=tx_pads,
|
tx_pads=tx_pads,
|
||||||
rx_pads=rx_pads,
|
rx_pads=rx_pads,
|
||||||
sys_clk_freq=self.clk_freq)
|
sys_clk_freq=self.clk_freq)
|
||||||
|
|
||||||
|
ad9154_spi = platform.request("ad9154_spi")
|
||||||
|
self.comb += ad9154_spi.en.eq(1)
|
||||||
|
self.submodules.converter_spi = spi_csr.SPIMaster(ad9154_spi)
|
||||||
|
self.csr_devices.append("converter_spi")
|
||||||
|
self.config["CONVERTER_SPI_DAC_CS"] = 0
|
||||||
|
self.config["CONVERTER_SPI_CLK_CS"] = 1
|
||||||
|
self.config["HAS_AD9516"] = None
|
||||||
else:
|
else:
|
||||||
raise ValueError
|
raise ValueError
|
||||||
self.submodules.rx_synchronizer = gtx_7series.RXSynchronizer(
|
self.submodules.rx_synchronizer = gtx_7series.RXSynchronizer(
|
||||||
|
Loading…
Reference in New Issue
Block a user