mirror of https://github.com/m-labs/artiq.git
sayma_amc: support uTCA backplane for DRTIO
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parent
8b939b7cb3
commit
d8b5bcf019
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@ -50,7 +50,7 @@ class SatelliteBase(MiniSoC):
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}
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}
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mem_map.update(MiniSoC.mem_map)
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mem_map.update(MiniSoC.mem_map)
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def __init__(self, rtio_clk_freq=125e6, identifier_suffix="", *, with_wrpll, **kwargs):
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def __init__(self, rtio_clk_freq=125e6, identifier_suffix="", with_sfp=False, *, with_wrpll, **kwargs):
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MiniSoC.__init__(self,
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MiniSoC.__init__(self,
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cpu_type="or1k",
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cpu_type="or1k",
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sdram_controller_type="minicon",
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sdram_controller_type="minicon",
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@ -68,15 +68,15 @@ class SatelliteBase(MiniSoC):
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clock_recout_pads = platform.request("ddmtd_rec_clk")
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clock_recout_pads = platform.request("ddmtd_rec_clk")
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else:
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else:
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clock_recout_pads = None
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clock_recout_pads = None
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# Use SFP0 to connect to master (Kasli)
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if with_sfp:
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self.comb += platform.request("sfp_tx_disable", 0).eq(0)
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# Use SFP0 to connect to master (Kasli)
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drtio_data_pads = [
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self.comb += platform.request("sfp_tx_disable", 0).eq(0)
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platform.request("sfp", 0),
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drtio_uplink = platform.request("sfp", 0)
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platform.request("rtm_amc_link")
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else:
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]
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drtio_uplink = platform.request("fat_pipe", 0)
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self.submodules.drtio_transceiver = gth_ultrascale.GTH(
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self.submodules.drtio_transceiver = gth_ultrascale.GTH(
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clock_pads=platform.request("cdr_clk_clean"),
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clock_pads=platform.request("cdr_clk_clean"),
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data_pads=drtio_data_pads,
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data_pads=[drtio_uplink, platform.request("rtm_amc_link")],
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sys_clk_freq=self.clk_freq,
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sys_clk_freq=self.clk_freq,
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rtio_clk_freq=rtio_clk_freq,
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rtio_clk_freq=rtio_clk_freq,
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clock_recout_pads=clock_recout_pads)
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clock_recout_pads=clock_recout_pads)
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@ -393,6 +393,8 @@ def main():
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parser.add_argument("-V", "--variant", default="satellite",
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parser.add_argument("-V", "--variant", default="satellite",
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help="variant: satellite/simplesatellite "
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help="variant: satellite/simplesatellite "
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"(default: %(default)s)")
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"(default: %(default)s)")
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parser.add_argument("--sfp", default=False,
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help="use SFP port for DRTIO instead of uTCA backplane")
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parser.add_argument("--rtm-csr-csv",
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parser.add_argument("--rtm-csr-csv",
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default=os.path.join("artiq_sayma", "rtm_gateware", "rtm_csr.csv"),
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default=os.path.join("artiq_sayma", "rtm_gateware", "rtm_csr.csv"),
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help="CSV file listing remote CSRs on RTM (default: %(default)s)")
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help="CSV file listing remote CSRs on RTM (default: %(default)s)")
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@ -405,10 +407,10 @@ def main():
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variant = args.variant.lower()
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variant = args.variant.lower()
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if variant == "satellite":
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if variant == "satellite":
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soc = Satellite(jdcg_type=args.jdcg_type, with_wrpll=args.with_wrpll,
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soc = Satellite(with_sfp=args.sfp, jdcg_type=args.jdcg_type, with_wrpll=args.with_wrpll,
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**soc_sayma_amc_argdict(args))
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**soc_sayma_amc_argdict(args))
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elif variant == "simplesatellite":
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elif variant == "simplesatellite":
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soc = SimpleSatellite(with_wrpll=args.with_wrpll, **soc_sayma_amc_argdict(args))
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soc = SimpleSatellite(with_sfp=args.sfp, with_wrpll=args.with_wrpll, **soc_sayma_amc_argdict(args))
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else:
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else:
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raise SystemExit("Invalid variant (-V/--variant)")
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raise SystemExit("Invalid variant (-V/--variant)")
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