mirror of https://github.com/m-labs/artiq.git
grabber: make parser EOP a pulse
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parent
701c93d46c
commit
d82beee540
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@ -34,8 +34,8 @@ class Parser(Module, AutoCSR):
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("a", 8),
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("a", 8),
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("b", 8),
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("b", 8),
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("c", 8),
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("c", 8),
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("stb", 1), # dval
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("stb", 1),
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("eop", 1), # ~fval (i.e. not together with stb)
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("eop", 1),
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])
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])
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# # #
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# # #
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@ -46,14 +46,14 @@ class Parser(Module, AutoCSR):
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lval = Signal()
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lval = Signal()
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fval = Signal()
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fval = Signal()
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dval = Signal()
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dval = Signal()
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last_lval = Signal()
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last_fval = Signal()
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self.comb += [
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self.comb += [
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Cat(dval, fval, lval).eq(cl[14:17]),
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Cat(dval, fval, lval).eq(cl[14:17]),
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pix.stb.eq(dval),
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pix.stb.eq(dval),
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pix.eop.eq(~fval),
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pix.eop.eq(~fval & last_fval),
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Cat(pix.a, pix.b, pix.c).eq(Cat(cl[i] for i in bitseq))
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Cat(pix.a, pix.b, pix.c).eq(Cat(cl[i] for i in bitseq))
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]
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]
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last_lval = Signal()
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last_fval = Signal()
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self.sync.cl += [
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self.sync.cl += [
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last_lval.eq(lval),
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last_lval.eq(lval),
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last_fval.eq(fval),
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last_fval.eq(fval),
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