From d80cf8d59d504dffa3c4cf9f122f4de6b8431b7a Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Tue, 31 Oct 2017 23:14:39 +0800 Subject: [PATCH] kc705: add TTLs and shift register driver for FMC DIO --- artiq/examples/master/device_db.py | 40 ++++++++++++++++++++++++----- artiq/gateware/targets/kc705_dds.py | 28 ++++++++++++++------ doc/manual/core_device.rst | 15 ++++++++--- 3 files changed, 66 insertions(+), 17 deletions(-) diff --git a/artiq/examples/master/device_db.py b/artiq/examples/master/device_db.py index d2a93bce6..b4c9c70ce 100644 --- a/artiq/examples/master/device_db.py +++ b/artiq/examples/master/device_db.py @@ -34,7 +34,7 @@ device_db = { "class": "DDSGroupAD9914", "arguments": { "sysclk": 3e9, - "first_dds_bus_channel": 29, + "first_dds_bus_channel": 32, "dds_bus_count": 2, "dds_channel_count": 3 } @@ -131,6 +131,34 @@ device_db = { "arguments": {"channel": 26} }, + # FMC DIO used to connect to Zotino + "fmcdio_dirctl_clk": { + "type": "local", + "module": "artiq.coredevice.ttl", + "class": "TTLOut", + "arguments": {"channel": 27} + }, + "fmcdio_dirctl_ser": { + "type": "local", + "module": "artiq.coredevice.ttl", + "class": "TTLOut", + "arguments": {"channel": 28} + }, + "fmcdio_dirctl_latch": { + "type": "local", + "module": "artiq.coredevice.ttl", + "class": "TTLOut", + "arguments": {"channel": 29} + }, + "fmcdio_dirctl": { + "type": "local", + "module": "artiq.coredevice.shiftreg", + "class": "ShiftReg", + "arguments": {"clk": "fmcdio_dirctl_clk", + "ser": "fmcdio_dirctl_ser", + "latch": "fmcdio_dirctl_latch"} + }, + # DAC "spi_ams101": { "type": "local", @@ -148,13 +176,13 @@ device_db = { "type": "local", "module": "artiq.coredevice.spi", "class": "SPIMaster", - "arguments": {"channel": 27} + "arguments": {"channel": 30} }, "ttl_zotino_ldac": { "type": "local", "module": "artiq.coredevice.ttl", "class": "TTLOut", - "arguments": {"channel": 28} + "arguments": {"channel": 31} }, "dac_zotino": { "type": "local", @@ -168,20 +196,20 @@ device_db = { "type": "local", "module": "artiq.coredevice.dds", "class": "DDSChannelAD9914", - "arguments": {"bus_channel": 29, "channel": 0}, + "arguments": {"bus_channel": 32, "channel": 0}, "comment": "Comments work in DDS panel as well" }, "dds1": { "type": "local", "module": "artiq.coredevice.dds", "class": "DDSChannelAD9914", - "arguments": {"bus_channel": 29, "channel": 1} + "arguments": {"bus_channel": 32, "channel": 1} }, "dds2": { "type": "local", "module": "artiq.coredevice.dds", "class": "DDSChannelAD9914", - "arguments": {"bus_channel": 29, "channel": 2} + "arguments": {"bus_channel": 32, "channel": 2} }, # Controllers diff --git a/artiq/gateware/targets/kc705_dds.py b/artiq/gateware/targets/kc705_dds.py index 983436aee..642c0ca44 100755 --- a/artiq/gateware/targets/kc705_dds.py +++ b/artiq/gateware/targets/kc705_dds.py @@ -98,35 +98,41 @@ _ams101_dac = [ ] _sdcard_spi_33 = [ - ("sdcard_spi_33", 0, + ("sdcard_spi_33", 0, Subsignal("miso", Pins("AC20"), Misc("PULLUP")), Subsignal("clk", Pins("AB23")), Subsignal("mosi", Pins("AB22")), Subsignal("cs_n", Pins("AC21")), IOStandard("LVCMOS33") - ) + ) ] _zotino = [ + ("fmcdio_dirctl", 0, + Subsignal("clk", Pins("HPC:LA32_N")), + Subsignal("ser", Pins("HPC:LA33_P")), + Subsignal("latch", Pins("HPC:LA32_P")), + IOStandard("LVCMOS33") + ), ("zotino_spi_p", 0, Subsignal("clk", Pins("HPC:LA08_P")), Subsignal("mosi", Pins("HPC:LA09_P")), Subsignal("miso", Pins("HPC:LA10_P")), Subsignal("cs_n", Pins("HPC:LA11_P")), IOStandard("LVDS_25") - ), + ), ("zotino_spi_n", 0, Subsignal("clk", Pins("HPC:LA08_N")), Subsignal("mosi", Pins("HPC:LA09_N")), Subsignal("miso", Pins("HPC:LA10_N")), Subsignal("cs_n", Pins("HPC:LA11_N")), IOStandard("LVDS_25") - ), + ), ("zotino_ldac", 0, Subsignal("p", Pins("HPC:LA13_P")), Subsignal("n", Pins("HPC:LA13_N")), IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE") - ) + ) ] class _NIST_Ions(MiniSoC, AMPSoC): @@ -254,13 +260,19 @@ class NIST_CLOCK(_NIST_Ions): rtio_channels.append(rtio.Channel.from_phy( phy, ofifo_depth=128, ififo_depth=128)) - phy = spi.SPIMaster(platform.request("sdcard_spi_33", 0)) + phy = spi.SPIMaster(platform.request("sdcard_spi_33")) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy( phy, ofifo_depth=4, ififo_depth=4)) - sdac_phy = spi.SPIMaster(self.platform.request("zotino_spi_p", 0), - self.platform.request("zotino_spi_n", 0)) + fmcdio_dirctl = self.platform.request("fmcdio_dirctl") + for s in fmcdio_dirctl.clk, fmcdio_dirctl.ser, fmcdio_dirctl.latch: + phy = ttl_simple.Output(s) + self.submodules += phy + rtio_channels.append(rtio.Channel.from_phy(phy)) + + sdac_phy = spi.SPIMaster(self.platform.request("zotino_spi_p"), + self.platform.request("zotino_spi_n")) self.submodules += sdac_phy rtio_channels.append(rtio.Channel.from_phy(sdac_phy, ififo_depth=4)) diff --git a/doc/manual/core_device.rst b/doc/manual/core_device.rst index 544337268..f67aea230 100644 --- a/doc/manual/core_device.rst +++ b/doc/manual/core_device.rst @@ -68,7 +68,13 @@ With the CLOCK hardware, the TTL lines are mapped as follows: +--------------------+-----------------------+--------------+ | 21 | LA32_P | Clock | +--------------------+-----------------------+--------------+ -| 28 | ZOTINO_LDAC | Output | +| 27 | FMCDIO_DIRCTL_CLK | Output | ++--------------------+-----------------------+--------------+ +| 28 | FMCDIO_DIRCTL_SER | Output | ++--------------------+-----------------------+--------------+ +| 29 | FMCDIO_DIRCTL_LATCH | Output | ++--------------------+-----------------------+--------------+ +| 31 | ZOTINO_LDAC | Output | +--------------------+-----------------------+--------------+ The board has RTIO SPI buses mapped as follows: @@ -86,11 +92,14 @@ The board has RTIO SPI buses mapped as follows: +--------------+--------------+--------------+--------------+------------+ | 26 | MMC_SPI_CS_N | MMC_SPI_MOSI | MMC_SPI_MISO | MMC_SPI_CLK| +--------------+--------------+--------------+--------------+------------+ -| 27 | ZOTINO_CS_N | ZOTINO_MOSI | ZOTINO_MISO | ZOTINO_CLK | +| 30 | ZOTINO_CS_N | ZOTINO_MOSI | ZOTINO_MISO | ZOTINO_CLK | +--------------+--------------+--------------+--------------+------------+ -The DDS bus is on channel 29. +The DDS bus is on channel 32. +This configuration supports a Zotino connected to the KC705 FMC HPC through a FMC DIO 32ch LVDS v1.2 and a VHDCI breakout board rev 1.0. + +The shift registers on the FMC card should be configured to set the directions of its LVDS buffers, using :mod:`artiq.coredevice.shiftreg`. NIST QC2 ++++++++