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test_cache: partially port to NAC3

This commit is contained in:
Sebastien Bourdeauducq 2022-02-26 17:56:02 +08:00
parent b9a359a45b
commit d7c915ff7b
2 changed files with 2 additions and 2 deletions
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1
artiq/coredevice/core.py
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@ -55,6 +55,7 @@ class Core:
self.dmgr = dmgr self.dmgr = dmgr
self.core = self self.core = self
self.comm.core = self self.comm.core = self
self.target = target
self.compiler = nac3artiq.NAC3(target) self.compiler = nac3artiq.NAC3(target)
self.embedding_map = EmbeddingMap() self.embedding_map = EmbeddingMap()

3
artiq/test/coredevice/test_cache.py
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@ -1,6 +1,5 @@
from artiq.experiment import * from artiq.experiment import *
from artiq.coredevice.exceptions import CacheError from artiq.coredevice.exceptions import CacheError
from artiq.compiler.targets import CortexA9Target
from artiq.test.hardware_testbench import ExperimentCase from artiq.test.hardware_testbench import ExperimentCase
@ -41,7 +40,7 @@ class CacheTest(ExperimentCase):
def test_borrow(self): def test_borrow(self):
exp = self.create(_Cache) exp = self.create(_Cache)
if exp.core.target_cls == CortexA9Target: if exp.core.target == "cortexa9":
self.skipTest("Zynq port memory management does not need CacheError") self.skipTest("Zynq port memory management does not need CacheError")
exp.put("x4", [1, 2, 3]) exp.put("x4", [1, 2, 3])
with self.assertRaises(CacheError): with self.assertRaises(CacheError):