test_cache: partially port to NAC3

artiq/coredevice/core.py

@@ -55,6 +55,7 @@ class Core:
         self.dmgr = dmgr
         self.core = self
         self.comm.core = self
+        self.target = target
         self.compiler = nac3artiq.NAC3(target)
         self.embedding_map = EmbeddingMap()
 

artiq/test/coredevice/test_cache.py

@@ -1,6 +1,5 @@
 from artiq.experiment import *
 from artiq.coredevice.exceptions import CacheError
-from artiq.compiler.targets import CortexA9Target
 from artiq.test.hardware_testbench import ExperimentCase
 
 
@@ -41,7 +40,7 @@ class CacheTest(ExperimentCase):
 
     def test_borrow(self):
         exp = self.create(_Cache)
-        if exp.core.target_cls == CortexA9Target:
+        if exp.core.target == "cortexa9":
             self.skipTest("Zynq port memory management does not need CacheError")
         exp.put("x4", [1, 2, 3])
         with self.assertRaises(CacheError):