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test_cache: partially port to NAC3
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@ -55,6 +55,7 @@ class Core:
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self.dmgr = dmgr
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self.core = self
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self.comm.core = self
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self.target = target
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self.compiler = nac3artiq.NAC3(target)
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self.embedding_map = EmbeddingMap()
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@ -1,6 +1,5 @@
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from artiq.experiment import *
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from artiq.coredevice.exceptions import CacheError
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from artiq.compiler.targets import CortexA9Target
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from artiq.test.hardware_testbench import ExperimentCase
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@ -41,7 +40,7 @@ class CacheTest(ExperimentCase):
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def test_borrow(self):
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exp = self.create(_Cache)
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if exp.core.target_cls == CortexA9Target:
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if exp.core.target == "cortexa9":
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self.skipTest("Zynq port memory management does not need CacheError")
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exp.put("x4", [1, 2, 3])
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with self.assertRaises(CacheError):
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