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artiq_ddb_template: fix pll_vco indentation

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This commit is contained in:
Sebastien Bourdeauducq 2019-02-22 23:50:30 +08:00
parent 62985fbd29
commit d79a6ee41c
1 changed files with 2 additions and 2 deletions
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4
artiq/frontend/artiq_ddb_template.py
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@ -177,7 +177,7 @@ class PeripheralManager:
name=urukul_name,
chip_select=4 + i,
uchn=i,
pll_vco=",\n\"pll_vco\": {}".format(pll_vco) if pll_vco is not None else "")
pll_vco=",\n \"pll_vco\": {}".format(pll_vco) if pll_vco is not None else "")
elif dds == "ad9912":
self.gen("""
device_db["{name}_ch{uchn}"] = {{
@ -194,7 +194,7 @@ class PeripheralManager:
name=urukul_name,
chip_select=4 + i,
uchn=i,
pll_vco=",\n\"pll_vco\": {}".format(pll_vco) if pll_vco is not None else "")
pll_vco=",\n \"pll_vco\": {}".format(pll_vco) if pll_vco is not None else "")
else:
raise ValueError
return next(channel)