M-Labs/artiq
2
0
Fork 2
mirror of https://github.com/m-labs/artiq.git synced 2024-12-18 16:06:30 +08:00
Code Issues Projects Releases Wiki Activity

wrpll.si549: initialize the clock divider to a sensible value

Browse Source
This commit is contained in:
hartytp 2020-10-07 10:11:25 +01:00 committed by Sebastien Bourdeauducq
parent e6ff2ddc32
commit d780faf4ac
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
artiq/gateware/drtio/wrpll/si549.py
View File

@ -255,7 +255,7 @@ class Si549(Module, AutoCSR):
self.gpio_out = CSRStorage(2)
self.gpio_oe = CSRStorage(2)
self.i2c_divider = CSRStorage(16, reset=2500)
self.i2c_divider = CSRStorage(16, reset=75)
self.i2c_address = CSRStorage(7)
self.errors = CSR(2)