2
0
mirror of https://github.com/m-labs/artiq.git synced 2024-12-20 00:46:30 +08:00

wrpll.si549: initialize the clock divider to a sensible value

This commit is contained in:
hartytp 2020-10-07 10:11:25 +01:00 committed by Sebastien Bourdeauducq
parent e6ff2ddc32
commit d780faf4ac

View File

@ -255,7 +255,7 @@ class Si549(Module, AutoCSR):
self.gpio_out = CSRStorage(2) self.gpio_out = CSRStorage(2)
self.gpio_oe = CSRStorage(2) self.gpio_oe = CSRStorage(2)
self.i2c_divider = CSRStorage(16, reset=2500) self.i2c_divider = CSRStorage(16, reset=75)
self.i2c_address = CSRStorage(7) self.i2c_address = CSRStorage(7)
self.errors = CSR(2) self.errors = CSR(2)