diff --git a/artiq/gateware/rtio/core.py b/artiq/gateware/rtio/core.py
index 6b19c52dd..4917a0371 100644
--- a/artiq/gateware/rtio/core.py
+++ b/artiq/gateware/rtio/core.py
@@ -89,6 +89,7 @@ class Core(Module, AutoCSR):
 
         outputs = SED(channels, glbl_fine_ts_width, "async",
             quash_channels=quash_channels,
+            lane_count=lane_count, fifo_depth=fifo_depth,
             interface=self.cri)
         self.submodules += outputs
         self.comb += outputs.coarse_timestamp.eq(coarse_ts)
diff --git a/artiq/gateware/rtio/sed/core.py b/artiq/gateware/rtio/sed/core.py
index ffade986a..df4e61b69 100644
--- a/artiq/gateware/rtio/sed/core.py
+++ b/artiq/gateware/rtio/sed/core.py
@@ -13,7 +13,7 @@ __all__ = ["SED"]
 class SED(Module):
     def __init__(self, channels, glbl_fine_ts_width, mode,
                  lane_count=8, fifo_depth=128, enable_spread=True,
-                 quash_channels=[], interface=None, report_buffer_space=False):
+                 quash_channels=[], report_buffer_space=False, interface=None):
         if mode == "sync":
             lane_dist_cdr = lambda x: x
             fifos_cdr = lambda x: x