test: fix test_dma

2018-03-04 23:19:06 +08:00 · 2018-03-04 23:19:06 +08:00 · d747d74cb3
parent 928d5dc9b3
commit d747d74cb3
1 changed files with 1 additions and 1 deletions
--- a/artiq/gateware/test/rtio/test_dma.py
+++ b/artiq/gateware/test/rtio/test_dma.py
@ -57,7 +57,7 @@ def do_dma(dut, address):
    yield
    while ((yield from dut.enable.read())):
        yield
-    error = yield from dut.cri_master.underflow.read()
+    error = yield from dut.cri_master.error.read()
    if error & 1:
        raise RTIOUnderflow
    if error & 2: